What's the difference between AHB, AHB1 and AHB2?

[MQi.1]

I read in reference manual and web tutorials of stm32f103c8, there were "AHB", "AHB1" and "AHB2", what's the difference between them, I know "APB1" and "APB2" are 2 APBs, the "1" and "2" are sequential numbers, how about "AHB1" and "AHB2" are they also sequential numbers, or mode type code for different level hardware standards?

[AScha.3]

 "AHB1" and "AHB2" are also sequential numbers . 

Just different specification than APB .  ("P" -> peripheral bus )

see:

https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture

>  Advanced Peripheral Bus (APB)

> High-performance Bus (AHB)

https://www.arm.com/architecture/system-architectures/amba/amba-specifications

[STOne-32 · Accepted solution]

Dear @MQi.1 ,

Our STM32F103C8/B   was the very first Cortex-M3 MCU made by ST and announced in public in 2007, the official documentation is here  : STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm®-based 32-bit MCUs - Reference manual  and you can see Figure 1 - It belongs to our Medium Density family and also then to Table 3 to see the mapping of Internal Bus : AHB and APB1 & APB2 .

We have no naming of AHB1 or AHB2 in that MCU and series,  But we introduced that different split in next generation for better system performance when we have different controllers such as Advanced DMAs and External memories to keep right bandwidth in high processing applications such as STM32F2/4/F7/H7   and of course others series.

As an example , in STM32F1 series - GPIOs are mapped on APB2 ( running up to 72Mhz in STM32F103C8) but then in STM32F2 or even STM32L1 we moved them to AHB for more performance at bandwidth level when running with concurrent peripherals .

Hope it helps you.

Cheers

STOne-32.