What is the proper method to interrupt/signal that new information is ready between core M7 and M4 in an STM32H7 processor?

[CodeRunner]

I am looking at the STM32H7 reference manual and STM32H745 code examples to determine how to transfer and signal new information between the cores. Currently I see two possibilities: Shared memory and a hardware semaphore/interrupt or shared memory and a software interrupt. If a hardware semaphore is used is it possible to initiate an interrupt from the CM7 core that is received on the CM4 core? I see that the hardware semaphore is primarily used to wakeup a sleeping CM4 core. From the ST provided dual core FreeRTOS example I see that they use a shared message buffer and a software interrupt to signal new information between the cores. Can a hardware semaphore be used to protect shared memory writes and signal new information between cores? Or is the FreeRTOS example the way with a software interrupt the proper way to share/signal information?

[Tesla DeLorean]

HSEM does some of the work, but you still need to manage the memory/cache coherency and write buffers if accessing common memories.