I am looking at the STM32H7 reference manual and STM32H745 code examples to determine how to transfer and signal new information between the cores. Currently I see two possibilities: Shared memory and a hardware semaphore/interrupt or shared memory a...
Our desire is to use the flexible PPS with fine correction for synchronization purposes. We are wondering if it might be possible to avoid the incorrect flexible PPS output interval with a quality grandmaster. Is it possible to get a clarification of...
I know that to get PPS output on the Ethernet PPS Pin PG8 that the device tree has to configure the pin for AF11. I also believe that PPS has to be enabled somehow? On some embedded Linux systems there is a /sys/class/ptp/ptp0/pps_enable variable to...
If it is possible is there an example or at least some guidance on how to implement the PPS output? Coming from Cortex-M4/RTOS development I am doing my best to learn Application Processor/Embedded Linux development.
I am having issues cross-compiling LinuxPTP. I've been able to work my way through some of the cross-compiling issues but now I am stuck with the compiler searching for crt1.o, crti.o and crtbegin.o files. Any help would be appreciated.
Yes, it also works for me in a Linux Mint virtual machine: java -version openjdk version "1.8.0_222" OpenJDK Runtime Environment (build 1.8.0_222-8u222-b10-1ubuntu1~16.04.1-b10) OpenJDK 64-Bit Server VM (build 25.222-b10, mixed mode)F...
I added PG8 in the ethernet0_rgmii_pins_a sections of the stm32mp157-pinctrl.dtsi in tmp-glibc/work sections for uboot-source and kernel-source sections. The I reran bitbake and put the image on the sdcard. Should that re-direct PG8 to the PPS signal...