What is the maximum pixel clock for LCD-TFT controller in STM32H723ZGT6?

[LauraCx]

Hello,

i would want to know the maximum pixel clock for TFT in STM32H723ZGT6. I have been looking at the AN4861 application note and tables 10 to 15 show the maximum pixel clock speeds for each family and configuration of pixel depth and ram memory. But I don't see any reference to the STM32H723ZGT6 chip family, which also has a TFT-LCD controller according to their datasheet. I don't know if this information is not provided or can be obtained in another way. 

@Alexis Rodríguez Jordán​ 

[Tesla DeLorean]

The 2-lane DSI implementations were 62.5 MHz for 16 bpp, and 41.67 MHz for 24 bpp

Generally the ceiling comes from the bandwidth of the frame buffer, so speed/width there, and presumably the expectation you want to interact or paint into the buffer too

[ARodr.16]

I don't quite understand your explanation. On the one hand, the configuration I would like to do is the connection of a TFT display with parallel RGB interface. I don't know if the maximum frequency will be the same for DSI or RGB interface. Also the TFT-LCD driver of this chip only handles RGB interface without additional hardware.

Regardless of this, the tables 10 - 15 I mentioned above give different values depending on the chosen configuration. For example with DMA2D enabled the value is lower, also using 2 layers, or with memories with a lower data bus. I can make sense of this behaviour, but as far as I can see there is no linear relationship and I don't know exactly where this data comes from. I guess it has to do with the latency and bandwidth of the peripherals and the SRAM memory.

The thing is that if the data doesn't appear I would at least like to know how to verify if my display would be suitable for this microcontroller, at the same time that the SRAM memory I want to install has enough bandwidth.

[AScha.3]

from ds :

[ARodr.16]

OK, I understand that according to the datasheet the maximum pixel clock speed is 150 MHz in those conditions. But I understand that's the maximum speed that the LTDC controller can handle. Then I guess the actual speed will depend partly on the SDRAM and bandwidth, but that would be another question. So I could say that the initial question is answered, but that leaves me with other questions. Anyway thanks for your answers.