What is a vector table and what information it contained while flashed with a OTA user application?

[MImda.1]

Hi,

I learned that when we flash a binary file to flash, we add the vector table with it. I want to know what is actually is a vector table.

I am actually working on uploading a .bin file to flash using IAP. verify it and jump to it. let's say while generating the .bin file using CUBE I state the start address is at 08005000. So if I flashed it using ISP it goes to the exact location. If a binary file doesn't contain any information header how the programmer knows where to flash it?

when I receive such a file through OTA how can I know the file size, starting address, and so on?

if the file was generated to work on 08005000 what if I flash somewhere else and jump to that location?

Thank you

[KnarfB · Accepted solution]

The vector table is an array of addresses. The very first entry is the initial stack pointer after reset, all others are addresses of exception / interrupt handlers (functions). The first handler (Reset_Handler) address is loaded by the MCU as initial program counter after reset. As the MCU hardware uses that array, it has to be at a well-known address in memory. There may be means in the MCU to adjust that (VTOR register...). Since the vector table contains absolute addresses (unless you patch it during download), the MCU will not work if you place the .bin file including the handlers at a different address.

The .bin file does not have any context, just machine code and global data. All other context must be implicitely known or you add some header providing it (base address, size, checksum,...).

[Tesla DeLorean]

Hopefully something covered by a Micro-controllers 101 course. Look for some college texts on computer/micro-controller architectures

ARM has Technical Reference Manuals (TRM) for the core.

ST Micro has Programming Manuals, and Joseph Yiu has some Essential Cortex-Mx books which put a more human perspective on the detail.

A Vector Table is a list of function addresses deeper into the firmware image, that the interrupt controller can select. See also how 68000 and x86 processors did this.

[MImda.1]

thank you @KnarfB​ and @Community member​  for a great explanation!!!