What happens when a STM32H747 encounters a skipped clock pulse on its HSE clock input every few million cycles?

[JanS]

I wonder if a regularly or sporadically missed clock pulse on the HSE clock input has any (negative) effect on the operation of the H7 processor or any clock output from a HRTIMER.

My guess is that the internal PLL might lengthen the next pulse a little bit and then shorten the pulse after this one a bit, or that it does not have any noticeable effect at all. Has anybody tried this yet or can shed some light on this?

Also would it be possible to detect lost pulses using the internal counters?

[Tesla DeLorean]

PLL is apt to absorb some, and duty cycle variations

>>Also would it be possible to detect lost pulses using the internal counters?

If you had a better clock, though the whole thing is mostly synchronous, so not exactly sure how you'd make it work with fast/wide counters.

You can free-run 32-bit TIM, the core has a DWT CYCCNT register

You could gate or latch via a 1PPS signal, but those often has 10's of ns of modulation/jitter