WDGA bit not immediately set after WWDG_Enable().

[MBoren]

STM32F405 using STLIBF4 v1.4.0

Near the beginning of my code, I enable the windowed watchdog with

WWDG_Enable()

Shortly thereafter, I have a conditional block that executes only if the windowed watchdog is enabled, i.e.

if ((WWDG->CR & WWDG_CR_WDGA) != 0)
{
     // do stuff
}

If this condition is checked immediately after the WWDG_Enable() call, the block fails to execute. However, if I move this conditional block later in the code (ensuring that some time has passed after enabling the watchdog), the block will execute as expected.

Through in-circuit debugging, I have confirmed that the WDGA bit in the WWDG_CR register does not read as set immediately after the execution of WWDG_Enable().

Please help me understand this behavior. Is the value of the WWDG_CR register only updated on the edge of PCLK1?

[waclawek.jan]

Not discussed in any great detail, but RM0090, 2.1.11 AHB/APB bridges (APB):

[...] Before using a peripheral you have to enable its clock in the 

RCC_AHBxENR or RCC_APBxENR register.

JW

[MBoren]

Great. Thank you for your patience. That should be enough information for me develop a solution.