Watchdog problem after FLASH_EraseSector

[franz2399]

Posted on February 22, 2012 at 17:09

Hi,

I use STM32F205RCT6 and attached you will find a sample for the STM320G-EVAL. Following problem. I have enabled the watchdog, but the FLASH_EraseSector takes much longer as the watchdog timeout. So I tried to reset the watchdog with the WWDG_IRQHandler. But the interrupt isn't called in this case! Reference Manual: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. And Watchdog cannot be disabled again except by a reset. Any ideas would be most welcome. Thanks #watchdog-flash-erase

[emalund]

Posted on February 22, 2012 at 18:46

the FLASH_EraseSector takes much longer as the watchdog timeout. So I tried to reset the watchdog with the WWDG_IRQHandler. But the interrupt isn't called in this case!

I have not 'investigated' this particular chip, but, typically flash erase will ''take over'' the chip.  Where you initialize the puppy, set it for a long enough time, flash erase is not THAT lenghty (see the datasheet). Erik

[Tesla DeLorean]

Posted on February 22, 2012 at 18:47

Quantify the erase time, and pick a bigger prescaler.

[franz2399]

Posted on February 23, 2012 at 07:40

Datasheet (Table 35. Flash memory programming)

Erase time for 128 KB Sector: more than 1 second Reference Manual (18.4 How to program the watchdog timeout): Watchdog Timeout values at 30 MHz (fPCLK1) Prescaler 8: Max 69.91ms So I can't set the timeout long enough. Thanks again

[Tesla DeLorean]

Posted on February 23, 2012 at 13:16

We'll your alternatives to that might be running all critical code in RAM, and not touching the FLASH, or do all your erase operations at reset prior to setting up the watchdog.

Things don't stop while erase/write operations occur, but if you read/execute from the array the CPU will stall (ie stuffed with wait-states) until the flash operation completes.

[emalund]

Posted on February 23, 2012 at 15:49

Watchdog Timeout values at 30 MHz (fPCLK1) Prescaler 8: Max 69.91ms

I do not (yet) know the f2, buy is 8 the highest prescaler divisor it has? also is PCLK1 the only clock available, in the F1 you can use the 40kHz ICLK. A separate clock for the WD is such a safety issue that I can not imagine they have dropped it for the F2 DO have a read Erik

[Tesla DeLorean]

Posted on February 23, 2012 at 18:34

The IWDG comes from a low frequency source, the WWDG comes from APB1 / 4096, so slowest tick rate is 915.5 Hz, with a 63-64 tick window.

I guess you could drop the APB1 clock rate. But anyway, when you are writing/erasing FLASH you're not going to be able to do any useful work unless you run totally from RAM. This is why you'd look to use an external FLASH or EEPROM, or use a device with multiple banks/planes that would permit concurrent operation. The STM32 design philosophy is for the FLASH to be read-only during normal operation. The fact you can run from it while erasing/writing is relatively unique.

[emalund]

Posted on February 23, 2012 at 19:45

<i>This is why you'd look to use an external FLASH or EEPROM, or use a device with multiple banks/planes that would permit concurrent operation.</i>

I've done many things involving flash erase and never wanted ''concurrent operation'' <i>The fact you can run from it while erasing/writing is relatively unique.</i> never knew a chip where you couldn't. You run from one sector and erase another. so, to the OP: set your puppy to use the LSI clock and you can get time enough to erase Erik

[Tesla DeLorean]

Posted on February 23, 2012 at 21:06

The F2 and F4 do not provide a method of clocking the WWDG from the LSI, it's APB1 / 4096, with the prescale of 1, 2, 4, or 8. I looked at the manual.

Virtually none of the 28Fxxx or 29Fxxx type NOR flash chips provide a method to read while programming, they generate a toggling status output till they are done. So totally NF and incapable of sustaining execution while that is occurring. Pretty much any CPU with flash as a multi-die attachment from ST or ATMEL fall into this category. A lot of systems side step this by copying data out of slow, narrow-bussed, NOR into SRAM before executing.

[emalund]

Posted on February 23, 2012 at 21:58

I have observed that there basically must be 2 kinds of flash.  I recall searching for a 2M*8  flash and looking at erase times.  When I saw the time for a SST flash I thought it was a misprint, the chip erase time was, approximately, as many milliseconds as the rest needed in seconds. 

It really surprises me that the F2 does not have the facility for a separate puppy clock some certifications require that. Oh, well you can't win them all. Erik