VREF+ not working as expected

aaron · ‎2014-09-03

Posted on September 03, 2014 at 19:53

Greetings all --

I have a custom board built around the STM32F303VC, which has separate pins for VDDA and VREF+. In the interests of keeping the voltage reference quiet, a 3.0V regulator is attached to VREF+, and VDDA is powered at 3.3V.

I am monitoring some input voltages that are scaled to 2.0V through resistor dividers. I have verified all of the voltages and they are where they should be.

The problem is this: all of my input voltages are reported about 10% lower than they should be. If I didn't know better, I would say that my reference voltage is still effectively 3.3V even though I know it is 3.0V.

I would expect, given an input voltage of 2.0V and a reference voltage of 3.0V, sampling 12 bits, I should get (2.0/3.0)*4095 = 2730 counts (or so). Instead, I am getting about 2510.

I have confirmed that all of the inputs are single-ended. The sample time is 7.5 cycles. I am scanning several channels with DMA every 40ms (triggered by a timer).

I cannot find anything that needs to be enabled in the firmware to use the VREF+ -- it looks like it should be automatic. Is there something else I should be doing to get the number of counts I expect? Is sampling from voltage dividers (with a series resistance ranging from 6K-133K Ohms) a problem? Any undocumented errata?

Thanks.

#stm32-vref+

aaron · ‎2014-09-03

Posted on September 03, 2014 at 20:12

I'll go ahead and respond to my own post.

It looks like the input impedance is the problem. The datasheet says that the maximum input impedance is 100KOhm, but it seems like having something even in the thousands of Ohms may be a problem.

I crudely connected a 1uF ceramic capacitor between each resistor divider and ground and saw a jump in the reported voltage almost immediately. It might be worthwhile to figure out the best values for the capacitor and the resistors, but I'm fairly sure that the VREF+ is working as desired. I just need to design in enough capacitance that the ADC doesn't pull the voltage down appreciably when the sample and hold pulls into its 5pF capacitor.