Using STM32 to replace old peripheral chip but it needs 8-bit parallel data bus to communicate with the Core like 8051

STM32 doesn't behave the way you want.

You could use a pin associated with a TIM_CHx, input capture mode, and having the DMA2 trigger from that same source, writing a word to GPIOx->ODR or GPIOx->BSSR

Not sure you could use EXTI to respond quick enough, you'd need to show expected interaction (full) with the 8051 via a timing diagram.

So you have 1us to respond to a command.

It would be tight, but you could use some amount of SPI/DUALSPI/QUADSPI in some configuration to read in data and respond.

Not sure on the FSMC questions.

You can use the FMC if you place a 74HC573 type octal latch between the STM32 data bus and the 8051. Write a byte to the latch, configuring the FMC as a SRAM/NOR flash type device. When the RD* strobe (combined with CS* if needed) from the 8051 occurs the latch output is enabled on falling edge. Use the RD* rising edge to an EXTI pin to signal the STM32 to write the next byte. This also gives you true tri-state connection to the 8051 data bus side, in case you have multiple devices on the bus.

For a block transfer use the RD* rising edge connected to a timer capture pin, as described earlier, as a DMA trigger to transfer the next byte to the latch. No IRQ latency with that approach, should easily handle 3MHz as long as the STM32 has a faster system clock to handle DMA and FMC latency.

Jack Peacock

Maybe you want to have a look at the new PSSI interface

https://community.st.com/s/question/0D50X0000C9eznY/parallel-synchronous-slave-interface-pssi-hosttohost-appnote-or-example

JW