2015-07-12 08:03 AM
Hello,
I'm currently working on simple device, which main task would be collecting data from ADC (via i2s) and sending them to base station via wireless (SPI based) transceiver.I'm planing to use STM32F103RCT6/8 series MCU.However it operates on so low clock and doesn't have I2SPLL module that I would be unable to provide MCLK signal for ADC/DAC on I2S. Is it possible to use MCO (Master Clock Output) signal, setup to 36MHz? Also would I2S slave SCK be in synch with this MCO signal as required by ADC?''Please note there is no required phase relationship, but MCLK, LRCK andSCLK must be synchronous.''Thank You for supportChris #i2s #stm32f1 #mco2015-07-12 09:35 AM
Can you output 36 MHz, Yes PLL/2
Will slaves to the same 36 MHz clock be synchronous, Yes.