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AJJ
AJJ
Associate II
August 4, 2023
Solved

Using Infineon HyperRAM with STM32L4R5

  • August 4, 2023
  • 9 replies
  • 3893 views

Hello,

I am looking for advice in using an Infineon S27KS0642 64Mb HyperRAM chip on a STM32L4R5Z and configured via CUBE.

I have it working, so I am pretty sure that the hardware is connected correctly and I can read and write successfully to it.  However, if I leave it for a while and then read again, the stored data is being corrupted (usually just single bits) and it gradually gets worse, as if the refresh isn’t working correctly.

My OctoSPI init function is shown below and I have a Peripheral SPI clock of 120Mhz.  Any advice would be very welcome.

Thanks

/* OCTOSPI1 init function */

void MX_OCTOSPI1_Init(void)

{

 

  /* USER CODE BEGIN OCTOSPI1_Init 0 */

 

    // release the beast...

    HAL_GPIO_WritePin(RAM_RST_GPIO_Port, RAM_RST_Pin, GPIO_PIN_RESET);

    HAL_GPIO_WritePin(RAM_RST_GPIO_Port, RAM_RST_Pin, GPIO_PIN_SET);

 

  /* USER CODE END OCTOSPI1_Init 0 */

 

  OSPIM_CfgTypeDef OSPIM_Cfg_Struct = {0};

  OSPI_HyperbusCfgTypeDef sHyperBusCfg = {0};

 

  /* USER CODE BEGIN OCTOSPI1_Init 1 */

 

  /* USER CODE END OCTOSPI1_Init 1 */

  hospi1.Instance = OCTOSPI1;

  hospi1.Init.FifoThreshold = 1;

  hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;

  hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS;

  hospi1.Init.DeviceSize = 23;

  hospi1.Init.ChipSelectHighTime = 7;

  hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;

  hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;

  hospi1.Init.ClockPrescaler = 3;

  hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;

  hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;

  hospi1.Init.ChipSelectBoundary = 0;

  hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED;

  if (HAL_OSPI_Init(&hospi1) != HAL_OK)

  {

    Error_Handler();

  }

  OSPIM_Cfg_Struct.ClkPort = 1;

  OSPIM_Cfg_Struct.DQSPort = 1;

  OSPIM_Cfg_Struct.NCSPort = 1;

  OSPIM_Cfg_Struct.IOLowPort = HAL_OSPIM_IOPORT_1_LOW;

  OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH;

  if (HAL_OSPIM_Config(&hospi1, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

  {

    Error_Handler();

  }

  sHyperBusCfg.RWRecoveryTime = 7;

  sHyperBusCfg.AccessTime = 7;

  sHyperBusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;

  sHyperBusCfg.LatencyMode = HAL_OSPI_FIXED_LATENCY;

  if (HAL_OSPI_HyperbusCfg(&hospi1, &sHyperBusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

  {

    Error_Handler();

  }

  /* USER CODE BEGIN OCTOSPI1_Init 2 */

 

    OSPI_HyperbusCmdTypeDef      sCommand = {0};

    OSPI_MemoryMappedTypeDef     sMemMappedCfg = {0};

 

    // Memory-mapped mode configuration

    sCommand.AddressSpace           = HAL_OSPI_MEMORY_ADDRESS_SPACE;

    sCommand.AddressSize            = HAL_OSPI_ADDRESS_32_BITS;

    sCommand.DQSMode                = HAL_OSPI_DQS_ENABLE;

    sCommand.Address                = 0;

    sCommand.NbData                 = 1;

 

    if (HAL_OSPI_HyperbusCmd(&hospi1, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

     {

     Error_Handler();

     }

 

    sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;

    //sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_ENABLE;

    sMemMappedCfg.TimeOutPeriod     = 1;

 

    if (HAL_OSPI_MemoryMapped(&hospi1, &sMemMappedCfg) != HAL_OK)

     {

     Error_Handler();

     }

 

 

  /* USER CODE END OCTOSPI1_Init 2 */

 

}

This topic has been closed for replies.
Best answer by Tesla DeLorean

The difference implied here is that they are a different die, with different / improved logic related to the OCTOSPI peripheral..

The P & Q parts are the same die, with HASH/CRYPT options fused OFF at final test, or an alternate metal layer/mask, to make the export issues go away.

9 replies

KDJEM.1
KDJEM.1
ST Technical Moderator
August 4, 2023

Hello @AJJ ,

It is mentioned in the errata sheet ES0393 -Rev10 and precisely 2.8.22 PSRAM not supported section that some reference manual and datasheet revisions unduly mention PSRAM while this type of memory is not supported by the device.
This is a documentation issue rather than a product limitation.

So, the Octal-spi PSRAMs memories SHOULD NOT be used with the STM32L4Rxxx and STM32L4Sxxx products.

In case of using Octal-spi PSRAMs memories I recommend you to use parallel PSRAMs with FSMC.

 When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on "Best answer" on the reply which solved your issue or answered your question.
AJJ
AJJAuthor
Associate II
August 7, 2023

Hello Kaouthar,

Thanks for your reply.

So, to be clear, are you saying that the OctalSPI HyperRAM PSRAM is supported on the STM32L4Pxxx and STM32L4Qxxx products, which, if I am reading datasheets correctly are pin-to-pin compatible with the Rxxx & Sxxx products?  The difference being the amount of normal RAM available.

 

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
August 7, 2023

The difference implied here is that they are a different die, with different / improved logic related to the OCTOSPI peripheral..

The P & Q parts are the same die, with HASH/CRYPT options fused OFF at final test, or an alternate metal layer/mask, to make the export issues go away.

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
Tesla DeLorean
Tesla DeLorean
Guru
August 4, 2023

hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; // Wrong if it needs a persistent clock

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
LCE
LCE
Principal II
August 7, 2023

Isn't there some register to set the "refresh interval" ?

At least for the H735 I found that in my source:

/* DCR4:
 * REFRESH = 500 NCS must be released, even for PSRAM for internal refresh 
 */
#define OSPI_HYPERRAM_REFRESH	500
OCTOSPI2->DCR4 = OSPI_HYPERRAM_REFRESH;
David Littell
David Littell
Senior II
August 9, 2023

Have you tried setting the .Init.Refresh to 100?  Works for me...(different HyperRAM device but this seems like it should be set properly ;)

Your .Init.ChipSelectHighTime seem a bit, uh, high.  Mine's set to 1.

Also try setting your .Init.ClockPrescaler to 1.  Is there any way in your device to get a faster clock to the OSPI block, say 333 MHz?  Your device parametrics indicate it wants to run at 166 and I haven't had the greatest of luck running HyperRAM devices slower than what's in their Data Sheets.

I would disable the delay block - I've never, ever seen any doc that clearly explains anything related to that thing and your hardware design should have trace lengths matched up.  If not, the delay block probably won't save you anyway.

 

AJJ
AJJAuthor
Associate II
September 1, 2023

The work-around is to use STM32L4P5ZGT6 instead of the STM32L4R5ZGT6

The big difference, however, is only 320K SRAM instead of 640K, but at least the HyperRAM works ! 

    Alex - APMemory
    Alex - APMemory
    Associate II
    October 10, 2023

    Just few more info

    - As mentioned in other chat, STM32L4R... is not supporting properly Octal RAM. This has been solved with STM32L4P... (you can refer to the disco for more info, https://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html) and other STM32 MCU

    - for info, some user which add no choice no possibilities to change MCU version and couldn't handle FMC/SDRAM/ADMUX high pin count, were able to run IoT RAM (APS6408L-OBM-BA) with STM32L4R9. Critical point is to avoid odd address write issue. In such case, you need to control your SW and access to the memory (at your own risk), either with direct simple access, or also for frame buffering (for example with a 2 bytes pixel, the DMA2D should be 2 bytes aligned, so no odd address access). As mentioned in previous reply, this is not supported by ST.

    Alex

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