Two VREF+ pins on STM32G474Q?

EThom.3 · ‎2025-04-02

When I first glanced through the STM32G474 datasheet, I saw VREF+ and VREF- on pins 43 and 44 on the LQFP128 package. "Cool", I thought, although I had no significant need for an actual VREF- pin.

However, when I was making a schematics symbol, I noticed that the two pins are in fact VREF+ and VREF+. Apparently, the exact same thing on two pins next to each other.

Does anyone know why this is? It makes perfect sense to have multiple pins for supply voltage and ground. But for a reference voltage? I have found no explanation in the datasheet or the reference manual.

This question was asked in another thread in December, but no answer was provided. Thread with original question:

https://community.st.com/t5/stm32-mcus-products/vref-stm32g474qe/m-p/750453

Edit: added screenshot

mƎALLEm · ‎2025-04-10

Hello all,

Our feedback regarding this subject:

The purpose to have two VREF+ pins is to decrease (to 1/2) the inductance of the bonding wires + lead frame. VREF+ is very sensitive to perfect decoupling (strong voltage) - but when the inductance of wire from pin to the pad on chip is too high then the VREF+ voltage on the die is not perfectly decoupled (there is large inductance). The inductance magnitude is too high on large packages - like LQFP128 (larger wires from pin to pad on chip). Smaller packages inductance is acceptable but for LQFP128 we should decrease this inductance and two VREF+ pins were designed there.

So it's recommended to connect both VREF+ pins externally (even they are internally connected).

I've already suggested (internally) to add a note on the pinout table 2 on both VREF+ pins to connect them externally.

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View solution in original post

mƎALLEm · ‎2025-04-02

Hello @EThom.3

Are you sure this is the correct link?

It doesn't mention any VREF+ pin problem.

Also check the package LQFP128 ?

Could you please share a screenshot of the issue?

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mƎALLEm · ‎2025-04-02

@mƎALLEm wrote:

Hello @EThom.3

Also check the package LQFP128 ?

OK I was pointing to another STM32G4 datsheet.

I will check internally about these two VREF+ pins on that package (I think one of them is VREF-). I'll get back to you as soon as I have an answer (Internal ticket 206667).

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EThom.3 · ‎2025-04-02

Yes. At least the link I provided works at my place. Erwin_N asks the question in the very last post in the thread:

Yes, the LQFP128 package is exactly what I intend to use. As I mentioned initially.

I have already shared a screenshot of the pin definitions table, but I am happy to share one of the package itself.

Just to summarise: Is there a particular reason that there are two VREF+ pins on this device?

EThom.3 · ‎2025-04-02

Thanks.

According to the datasheet, VREF- is connected to VSSA. But in case one of the pins really is VREF-, it would be crucial to know which is which.

It seems a bit unlikely that no-one has raised the issue before, if that is really the case.

mƎALLEm · ‎2025-04-02

@EThom.3 wrote:

Just to summarise: Is there a particular reason that there are two VREF+ pins on this device?

No. I don't think so. Most probably it's a typo and one of them is VREF-.

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MasterT · ‎2025-04-02

Data sheet clearly states that VFRE- is bounded to VSSA, so the reason why two VREF+ I'd think to separate VREF for manny internal analog consumers, ADC/ DAC-slow/ DAC-fast/ OPA/ COMP.

Can you measure resistance between pin 43 & 44, when IC is unpowered?

EThom.3 · ‎2025-04-02

I don't have a device yet. I am in the beginning of the schematic drawing phase.

mƎALLEm · ‎2025-04-02

@MasterT wrote:

Data sheet clearly states that VFRE- is bounded to VSSA, so the reason why two VREF+ I'd think to separate VREF for manny internal analog consumers, ADC/ DAC-slow/ DAC-fast/ OPA/ COMP.

If it's the case need to separate the names VREF1+/VREF2+ for example.

But need to have a clarification from the internal teams.

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MasterT · ‎2025-04-02

I find stm32g474QET6 on STM32G474E-EVAL evaluation board, schematics indicates that 43 & 44 externally connected.

Chances both pins likely connected inside as well, than reasoning to minimize inductance/ resistance/ interference in between analog peripheral devices. 15 msps DAC's potentially could significantly impact adc SNR performance.