Capacitor for VREF pin on SMT32L4P5CG MCU

[Aldo_Flores_Aguayo]

Hi, I´m beginner in SMT32 MCU design, I´m doing a design for the above MCU and in the document "AN4555" that is for hardware develoment of these MCU series I founf that

So for my package (64 pins) the VREF and the VDDA power signals are bounded inside the MCU, and I only have the VDDA pin available on my package,  then the AN4555 states that if the these power signals (VREF and VDDA) are internally bounded I need a 1uF capacitor on this pin, so in this case I need to place a capacitor on the VDDA pin? 

And for another side if the decoupling recommedation for the VDDA pin is to place a 1uF it´s necessary to add another 1uF capacitor because on this pin (VDDA)  there is the VREF power signal bonded internally?

[STOne-32]

Dear @Aldo_Flores_Aguayo ,

That note ( Yellow) is not referring to VDDA internally bounded to VREF+ , this for package that have a separate VREF+ ( 100 pins as examples) and we can route to internal VREFBUFF reference .

in Your case with package 64 pin : you need only 1uF and 100nF on that pad . 
Hope it helps you ,

STOne-32

[Aldo_Flores_Aguayo]

Thanks for reply @STOne-32  and sorry but I´m still confused, I already check that my MCU package doesn´t have a specific VREF+ pin exposed as mentioned here 

Then looking at the pinout of my package for 48 pins ( I got confused in previous post and thought it was 64 pin sorry for that) 

it shows this on pin 9: VDDA/VREF+ does that mean these power signal are bounded insede the MCU in first place? 

If that is the case do I need to place the 1uF capacitor on pin 9? 

Note: The recommendation for VDDA pin decoupling alredy include a 1uF and because the VDDA and VREF+ are in the same pin (al least is what I undertood) that means two 1uF capacitors need to be placed on that pin one for VDDA and one for VREF+? 

Sorry I hople I explain my self in a better way. 

Thanks for your time.