Trying to access STM32L072CZ AHB2 addresses from SWD

[NKA]

Hi,

New to STM32 I'm discovering the STM32L072CZ, I'm trying to access the AHB2 bus by SWD interface in order to r/w on addresses (say 0x4800 0000 on peripheral GPIOA). When performing a coresight read on 0x48000000 I got 0xBC11477.

After checking Ultra-low-power STM32L0x2 advanced Arm®-based 32-bit MCUs - Reference manual page 56/1009 it says "After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register."

I have no clue how to access RCC_AHBENR since RCC is defined on AHB1.

Trying to read on the boundary address 0x40021000-0x400213FF gives in cycle 0xbc11477 0xf0000040 (unspecified error) 0x0... I don't know what does that mean.

Am I on the right way ? thanks.

[waclawek.jan · Accepted solution]

There is no AHB2 in the 'L0, there's only one AHB bus. The 0x4800'0000 address is not mapped. GPIOA is on the private bus (IOPORT) of the processor at address 0x5000'0000. 0xbc11477 is the SW-DP ID (see SW-DP state machine (reset, idle states, ID code) chapter in RM and the referred ARM documentation), so you probably don't read the mcu's bus.

JW

[NKA]

My bad... was reading stm32f030rc.pdf at the same time...

Indeed Ultra-low-power STM32L0x2 advanced Arm®-based 32-bit MCUs - Reference manual shows GPIOA on 0x5000'0000 - 0x5000'03FF on IOPORT private bus.

Thanks