TIMx TRGO generation

[Andrei Chichak]

Posted on March 28, 2017 at 23:39

On my '407 I am using TIM2 to trigger a series of ADC conversions. The connection between TIM2 and the ADCs is TRGO.

I have set up the time base for TIM2 to be 84MHz and TIM2 has no prescaler and a counter period of 21,000.

I expected that this would give me 84M/21K = 4000 conversions per second.

I seem to be getting closer to 117.

Is there a /32 stage on TRGO?

I can't find any documentation that describes the generation of TRGO. And since it bypasses the compare registers, the match criteria is hidden in the trigger controller section.

Thanks,

Andrei

[Tesla DeLorean]

Posted on March 28, 2017 at 23:56

TRGO needs to be set to Update, or CCx, to create an association. No divisor or prescaler I'm aware of, ClockDivision impacts the pin filters/sychronizers

117 suggests it is running from an 25 MHz HSE, and likely not the PLL, so check it hasn't fallen out of the clock setting code, or that some other code hasn't been called.

21000-1

[Andrei Chichak]

Posted on March 29, 2017 at 00:12

It's definitely not the PLL. I have MCO1 and 2 saying that the processor is running at 168MHz.

What command do you use to set TRGO to Update? (I can work that back in Cube or stuff in the proper command).

-1!

A

[Andrei Chichak]

Posted on March 29, 2017 at 00:14

Found it. and it's set to Update. 

A

[Andrei Chichak]

Posted on March 29, 2017 at 00:27

The ratio seems to be like /34.

A

[Tesla DeLorean]

Posted on March 29, 2017 at 01:57

Pretty bizarre, you have the PLL at MCO, or SYSCLK?

Anything odd with DMA buffer length, channels, are you toggling LED with ADC EOC?

Cube/HAL oddness? I've done SPL base TIM TRGO into the ADC (TIM+DMA), can't say I've seen x34 decimation.

Is the HSE 25 MHz on this system?

[Andrei Chichak]

Posted on March 29, 2017 at 02:16

As it turns out, YES, I have MCO1 feeding out PLLCLK and MCO2 feeding out SYSCLK. Both verified on a Tek o-scope.

APB1 timers clock is set to 84MHz,

HSE is the 8MHz crystal on a F4Discovery board.

Oddness in the DMA? Hmm, I have ADC1 and 2 set up for simultaneous conversions, 10 on ADC1 and 7 on ADC2. I am pulsing an LED on DMA half and complete on a circular buffer. One conversion sweep per DMA transfer.

OOOOOHHHHhhhh, I wonder if I'm not generating enough data to satisfy the DMA transfer. THAT would do it.

Something to check in the morning.

Thanks for the rubber duck.

A

[Tesla DeLorean]

Posted on March 29, 2017 at 03:46

With a single DMA? Thought they needed to be symmetrical? Pulling a 32-bit word from CDR

10+7= 17, 17*2 = 34, seems a bit of a coincidence

[Andrei Chichak]

Posted on March 29, 2017 at 03:57

It certainly does. I bet that, instead of getting 17 results per tick, I'm getting one. To fulfil the request it needs 17 words and I bet I'm getting 1 half-word.

That adds up. All the evidence makes sense. I must have an issue with how I'm starting the ADC and its not picking up the conversion layout properly. Luckily I have another, working (?), program that I can spelunk and see what I screwed up.

A