2022-04-07 07:22 PM
We make below code.
The variable a is written from both main function and interrupt function.
When accessing variable a with the main function to realize exclusive control, interrupt disable and enable (__disable_irq(), __enable_irq()) are used.
How long does it take from the execution of the interrupt disable function to the reflection on the CPU at this time?
Or is there a mechanism to access the variable a after the interrupt disable is reflected in the structure of the CPU?
If there is a manual regarding the behavior after executing the interrupt prohibition function, please let me know.
Solved! Go to Solution.
2022-04-12 05:03 PM
> We can rest assured that there is somewhere in the text that shows that the above is guaranteed.
https://developer.arm.com/documentation/dai0321/latest
Section: "4.8 Disabling interrupts using CPS and MSR instructions". Also I recommend reading at least sections 4.5-4.9, especially the 4.9.
2022-04-07 08:33 PM
What chip family? You can find cycles per instruction on the M0 and M4 cores, but the M7 core is not as simple to calculate. Even on the M0/M4 cores it is not always straightforward.
https://developer.arm.com/documentation/ddi0439/b/CHDDIGAC
Keep in mind the compiler is free to rearrange/optimize as it sees fit. Use volatile if you don't want a variable optimized out.
2022-04-07 10:02 PM
@TDK
Thank you for answering.
Currently We use M4 cores.
Even if interrupt disable is set in the register using __disable_irq(), We are concerned that variables will be accessed from the main function and interrupt function at the same time during the delay until the CPU actually disables interrupts.
2022-04-07 10:14 PM
2022-04-07 10:24 PM
I think it takes a few CLKs to write the disable_irq register and it works.
If main function are interrupted between a few CLKs, program cause unexpected behavior.
>>Gating access to a variable within those calls is sufficient to ensure no >>interrupts will be called or access it at the same time.
We can rest assured that there is somewhere in the text that shows that the above is guaranteed.
2022-04-08 08:04 AM
If your application is as simple as your example code, you can't have the behavior you describe.
Are you sure you don't use a disable/enable pair in a function called from inside a protected code?
Using __disable_irq() / __enable_irq() is dangerous.
You must save the PRIMASK before you disable, and restore PRIMASK to enable again.
2022-04-12 05:03 PM
> We can rest assured that there is somewhere in the text that shows that the above is guaranteed.
https://developer.arm.com/documentation/dai0321/latest
Section: "4.8 Disabling interrupts using CPS and MSR instructions". Also I recommend reading at least sections 4.5-4.9, especially the 4.9.
2022-04-12 05:34 PM
Thank you for answering.
We read this section, and This is what we were looking for.
We will use __disable_irq() and __enable_irq() with confidence from now on
2022-04-12 05:37 PM
That's right.
We need to check the PriMask in the actual code.