Timer synchronization maximum frequency

[NArnd]

Hi,

If I am starting with 120 MHz system clock and want the master timer to generate a 60 MHz PWM waveform and I want the second timer to generate an in-phase 8 MHz PWM waveform I must clock the second timer with 120 MHz (as 60 MHz isn't divisible by 8). Can this be achieved by configuring the first timer to generate TRGO from ENABLE and configuring the second timer in GATED_MODE from TRGI? (Or is this self-evident?)

Best regards

Niclas

[waclawek.jan]

Which STM32?

You want the slave in Trigger mode.

JW

[NArnd]

Hi,

Thanks JW. Now I see the way to use trigger mode.

It's STM32L4R7ZIT6. APB1 and APB2 both on 120 MHz.

In total I'm currently looking at TIM1 as the master and TIM4, TIM8, and TIM2 as slaves, all starting at the same time as TIM1.

(Or alternatively to have TIM1 be master to TIM2 and TIM4 be master to TIM8 but no synchronization between the two pairs.)

Just out of curiosity: Could gated mode be used in my case? Does gated mode require that the TRGI signal be high before the APBx clock rising edge that actually 'starts' the counting? Or are both of these signals acting as triggers for the counter so it doesn't matter which one arrives first?

What effect does the TIMx_SMCR MSM bit have? I'm looking both at the L4+ RM0432 rev6 and AN4013 rev8 but am slightly confused. Is TRGO delayed when the master is started by a register write (as opposed to the trigger input).

"When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." (RM p1260)

Best regards

Niclas

[waclawek.jan]

I don't know what is exactly the relationship between TRGI and input clock in context of gated mode.

Effect of MSM is IMO described inadequately - it does not delay TRGO, it delays effect of TRGI on starting the timer. I never tried but I believe the hint that this does not work on manually enabled time. I wouldn't hold my breath expecting this mechanism to work correctly across timers on different APB buses, especially if they run at different dividers.

I am not ST. For more intimate details you may want to contact ST directly, through web support form or FAE.

JW

[NArnd]

Thanks again JW.