Timer Preload and Shadow registers

[dsjnews]

Posted on June 28, 2012 at 12:38

Hi,

I am trying to get a better understanding of the timer hardware for the advance control timers. In section 14.3.1 of RM0008 (Rev. 14) it states:- ''The auto-reload register is preloaded.Writing to it or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or ......'' Neither the 'preload' register or 'shadow register' appears on the block diagram but are referenced quite frequently in the document, so I have the following questions. (a)    Why is there a need for the preload register? (b)    Why is there a need for the shadow register? For each timer is there just a single shadow register? Regards Jo.

[Tesla DeLorean]

Posted on June 28, 2012 at 13:22

Consider that the timers can run twice the APB clock rate, and an access will take 4 APB cycles.

[dsjnews]

Posted on June 28, 2012 at 16:32

I think I am still missing it here.

Could you give me the sequence of events that occurs when I write a new value to ARR in terms of the preload, shadow and CNT registers?

[Tesla DeLorean]

Posted on June 28, 2012 at 17:02

I'm going to preface this by stating that I don't have a gate level understanding of the STM32 design.

The description provided seems to indicate that the timers have staging registers to mitigate the fact you are trying to read/write registers whose values change at a much higher rate. So that you update once, and that you don't get meta-stability issues (ie violating setup/hold timings), and that you don't see critical path/skewing (ie some bit paths and transition occur more rapidly/slowly than others). Here the content of the counter gets latched into a staging register in one TIMCLK cycle, atomically, and then that value can be read by a much more leisurely bus, without any concern of the value changing. The register being read is not the counter itself, and the counter may already have incremented, or wrapped. On the writing side the value is staged, and on completion of the bus cycle the value is forwarded to the target register in a single TIMCLK cycle.

[Tesla DeLorean]

Posted on June 28, 2012 at 17:17

Photography analogy

Take a picture of a wall clock with an 8 second exposure. The picture will have the second hand smeared across an 8 second duration. The minute, and hour hands might also appear in two locations depending when you catch the clock. Gets worse with a 16-bit binary counter, ALL the bits might transition during the longer observation window.