Timer cross-influence on STM32F302VCT6

[ABati]

Hello,

We have noticed an issue with the master-slave mode in the timers on STM32F302VCT6.

We use TIM1 to generate PWM signals, and TIM15 for triggering an ADC.

The issue is that there is cross-influence from TIM15 to TIM1. (Can be seen on the attached picture).

We have made a minimal application to rule out the rest of our code having influence. The code is also attached.

Other observations:

By default TIM1->SMCR is 0x0, hence SMS is 0 (Slave mode disabled). However, TS is also 0, mapping the master to TIM15. Still there should be no influence.

If we change the TS to 0x1 (master should be TIM6, SMS still 0, so slave mode should be disabled), there is no cross-influence.

However, if we change TIM15 to TIM6 in this case, the cross-influence is there again.

Conclusion: TIM1 always acts like it is in slave mode, no matter what the SMS is.

We did not do similar tests with other Advanced Timers (8 and 20).

Regards,

Aleksandar Batinica

[waclawek.jan]

What do we see on that picture?

What is the expected behaviour, and why do you think other timers influence it?

JW

[ABati]

Hi, sorry for the lack of information. What you see ​is a PWM pattern on 6 channels (TIM1) being distorted at the points where the second timer (TIM15) reloads. there are measurements between two distortions that exactly align with the reload frequency of TIM15. If we change the reload value of the timer, the period between distortions mirrors it.

The expected behaviour is to have a continuous, non-distorted pwm ​signal, of constant duty cycle.

[waclawek.jan]

> sOutputCompareConfigPWM.OCFastMode  = TIM_OCFAST_ENABLE;

Try disable.

JW

[ABati]

Thanks, it fixed the issue. Although I still can't see this documented correctly in the user manual. Looking at the detailed timer schematic. I do not see a pathway for the trigger signal to reach the OC block with the given settings.