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Timer: clearing update event flag can cause flagless input capture interrupt

dhaselwood
Associate II
Posted on October 22, 2011 at 20:31

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The goal is to measure durations between input captures that exceed the 16 bit counter range by adding counter overflows. There appears to be no way to cleanly do this.  The basic problem is that clearing the update-event interrupt flag is a read-modify register-write type of operation.  During that short window a signal that causes an input capture will turn on the input capture flag, and then have it immediately reset by the write operation that is clearing the update-event flag.  The result is that an input capture interrupt follows, but there will be no flag set.

This situation is rare, but I have caught instances of it happening.  In my particular case I am able to treat an input capture interrupt with no flag set the same as if the flag were set and the results are correct, however in the general case this would not work when more that one input capture in a timer was being used as the routine would not be able to tell which channel was the cause of the flagless interrupt.

Is the some way around this problem? Might DMA avoid the problem, (if the DMA channels are not tied up!)?

#input-capture #timer
12 REPLIES 12
rmteo
Associate II
Posted on October 23, 2011 at 23:45

http://www.rowley.co.uk/arm/index.htm

with ST-Link and J-Link (Kinetis KwikStik).

dhaselwood
Associate II
Posted on October 25, 2011 at 17:19

dhaselwood
Associate II
Posted on October 25, 2011 at 17:24

Would the use of bit-banding take care of the problem? 

The problem is that reading a register, masking the interrupt flag bit, then writing back to the register allows a window for other interrupts to appear, then get erroneously reset.  Bit-banding operates at the big level and should take care of the problem'