TIM2 encoder mode - please help !

[mehmet.karakaya]

Posted on October 05, 2010 at 15:20

TIM2 encoder mode - please help !

[John F.]

Posted on May 17, 2011 at 14:10

Thanks for the response. I'm pressing for more of an answer because I genuinely don't understand. Programming Manual 15491.pdf says (2.3.5)

If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. and (2.3.6) Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler, If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. I like things determinate! Why should, ''things not work correctly'' until the preemption and sub-priority levels are unique? re YMMV ... My mileage SHOULDN'T vary!

[Tesla DeLorean]

Posted on June 04, 2012 at 03:38

I guess my problems here are that you can create a situation where one service routine can repeatedly tail chain to the exclusion of others as there is not any rotation.

Secondly that if dependencies are created in a specific service order you can run into problems when the underlying system subtly changes. Say you've designed a system using an STM32 without a TIM5 peripheral, and are using USART1 & 2 and TIM4 in some contrived way, somewhere down the road someone changes chips and needs TIM4 for some other purpose because they can escape the pins, and moves the design to use TIM5 for the USART1 & 2 handling. Now all of a sudden we have TIM5 with an interrupt number that is much bigger, and the other side of USART1 & 2, and things start operating strangely. Now yes this is a bit contrived, but I've seen people build these kind of meta-stable systems, which have dependencies they don't understand or communicate, and they complain about the hardware being buggy. If a design is truly agnostic to priority/preemption then test it with everything inverted, and if a design has dependencies then express them, and rigidly define them, and do so in a manner that is agnostic to the peripheral choice or pin usage.

[Kasapoglu.Orkun]

Posted on July 25, 2012 at 14:39

must handler be as your codes? is this wrong??

void TIM2_IRQHanler (void) { TIM_ClearFlag(TIM2, TIM_FLAG_Update); GPIO_WriteBit(GPIOD, GPIO_Pin_15, Bit_SET); delayxs(200000); GPIO_WriteBit(GPIOD, GPIO_Pin_15, Bit_RESET); delayxs(200000); }

[Tesla DeLorean]

Posted on July 25, 2012 at 19:33

Per your other thread, you have a typo in the function name, and consequently no linkage to the vector table dispatching the interrupt.

[FF1]

It will be also useful for others if you can post your working code because it seems more people have same trouble.

Thank

Fabio

[FF1]

It will be also useful for others if you can post your working code because it seems more people have same trouble.

Thank

Fabio

[Tesla DeLorean]

This ones from 7 years ago, please stop and think about how to solve this without pulling ghosts of forums past.

These people were using SPL, likely on different parts.

Are there no more recent examples for encoders you can use?

TIM_EncoderInterfaceConfig

https://community.st.com/s/question/0D50X00009XkibnSAB/stm32f107-quadrature-encoder-example