TIM2 CH2 output on 2 GPIO's

[danielbathtub]

Hi, 

For my application I need to output the same signal on 2 different IO Pins. 

I need to use a timer because the signal has to have extremely accurate timing. 

As a first iteration, I allocated 1 GPIO pin to TIM CH2 and the other GPIO Pin to TIM CH3. 

I then asked myself the question of why am I wasting a timer channel 3 (which I could desperately use for other things). If the 2 signals will always be the same, why not just take another GPIO pin and write set the alternate function regitsers also to TIM2 CH2, obviously that will then change the specific IO Pin. But that doesn't concern me at this stage of development. 

I then did this, and it works. I outputted the waveform from Timer 2 Channel 2 on two IO Pins simultaneously. I used Register Access level code to do this. 

For interest sake, I wanted to then change a IOC file in CubeIDE to do the same thing I mentioned above and it's impossible. CubeIDE prevents me from doing this using their IOC settings. I don't care because I don't use any external libraries in my software and my application doesn't rely on anything from the IOC file. But I am curious if someone has an explanation as to why this happens ?. Is it not supposed to be possible in the silicon ?. 

Thanks. 

[waclawek.jan · Accepted solution]

ST does not allow setting two or more pins to the same AF (and in some RMs there's a sentence which is forbidding this, even if its wording is cumbersome), presumably for them to allow flexibility in the implementation.

In other words, you may find it is working, but you shouldn't rely on it.

JW

[Bob S]

@waclawek.jan That note is poorly worded, at least as it appears in the RM0090 (STM32F4xx) reference manual.  But I interpret that note as meaning that a single GPIO pin can only be connected to one peripheral function at a time.  Which is (or should be) obvious from the GPIO_AFRL and AFRH register descriptions).  I don't see it preventing multiple GPIO pins from being connected to the same peripheral function.

[danielbathtub]

Yes, I looked into the STM32G0x series reference manual. It simply stated that there is a multiplexer connected to each IO Pin that multiplexes between the different alternate functions to prevent between a conflict between alternate functions. It then states that only one alternate function at a time can be connected to an IO Pin. No mention of one alternate function connected to more than one IO Pin. 

[waclawek.jan]

@Bob S, @danielbathtub ,

> That note is poorly worded

> I don't see it preventing multiple GPIO pins from being connected to the same peripheral function.

I know.

We've discussed this here in the past several times, and one of the Moderators once came back quoting this note - unfortunately I haven't stored link to that discussion.

I am not ST so all I can offer is the observation described in the article I've linked above, and a warning, that that's just my observation.

What I think is, that while the STM32 designers usually do things in this way, it's not an official design guideline, so that there may be undocumented exceptions and the only guaranteed thing is that if you connect one IP pad to one pin in the matrix. Again, I am not ST and this is just my speculation.

JW