GPIO output pulse stability (bis)

[Lorenzo38]

Hello,

Trying to do precise GPIO pulses with assembly code - on any STM Nucleo board - shows jitter and fluctuating frequency. I was told by a super user to do it via PWM

I would like to add some comment that may be interesting for others :

- trying to do precise pulses with PWM on the Nucleo H723 for example, still shows jitter and fluctuating frequency around the desire value. Same using HSE or HSI. Same with Nucleo-F411. Same with Nucleo-N667. I understand the reasons now.

But playing around the Nucleo-N657, I got some success : if you feed your CPU_clock directly with HSE (48MHz on board), and feed the other peripherals, including timer_clock with HSE+PLL (400MHz for example), then the resulting PWM is quite accurate and stable !

Regards,

[Andrew Neil]

You're referring to this thread: GPIO output pulse stability - yes?

[TDK]

The reason this is happening is that "HSE Bypass" is driven from the incoming clock signal. On the NUCLEO-H723ZG this is an 8 MHz signal driven by the HSE within the ST-LINK. So it will have the same jitter as HSI.

The user manual goes into some detail about this.

This is in contrast to the NUCLEO-N657X0-Q where the default HSE is the onboard crystal. Again, the user manual covers this:

[gbm]

Hard to believe really. Double check the clock configuration of your project. The PWM output frequency stability & jitter should be and ARE exactly the same as MCU clock input parameters. On most of Nucleo boards (excluding STM32L series ones) it is possible (but not obligatory) to use 8 MHz clock from ST-Link (8.33 MHz option is available but not default on Nucleos with ST-Link 3). On newer ones (C0, H5, ...) onboard HSE oscillator or generator is included.

If you use HSE as input clock, the only jitter and instability you may encounter originates from PLL and should be neglectable & hard to measure.

@TDK: AFAIK, ST-Link output clock is generated by its crystal-driven HSE, so it should be pretty good.

[TDK]

> AFAIK, ST-Link output clock is generated by its crystal-driven HSE, so it should be pretty good.

@gbm On ST-Link V2 chips where the st-link uses a 8 MHz crystal, you would be correct. On the STLINK-V3E (which the NUCLEO-H723ZG has), the ST-Link chip uses a 25 MHz crystal and can't do this. There are a variety of outputs, but the default (8 MHz) is derived from the HSI.

Overview of ST-LINK derivatives - Technical note

[Lorenzo38]

Yes Andrew, I'm refering to my previous post : GPIO output pulse stability

[Lorenzo38]

Thanks for your comments, and I know the different clock sources for the various boards (as said in manuals)

All the boards I've tested which have HSI or "derived" HSE (= coming from the STLINK quartz) make noisy PWM.

All the boards I've tested which use "true" HSE (= quartz on board for CPU), but from which clock_CPU and clock_timer come from PLLs make also noisy PWM.

On the N657, you can get the clock_CPU directly from the quartz (=48MHz), and the clock_timer from the PLL (=up to 400MHz). In this configuration, the PWM is stable.

Regards,