TIM1 configuration and it's behavior

pawelcit · ‎2011-12-27

Posted on December 28, 2011 at 02:30

Hi, first of all sorry for my english but I hope you will understand me.

Here is a TIM1 configuration form DSO nano project. I've rewrited it to more readable format:

TIM1->PSC = 30;

TIM1->ARR = 35;

TIM1->CCR1 = (35+1)/2;

TIM1->CR1 = TIM_CR1_DIR | TIM_CR1_URS | TIM_CR1_ARPE;

TIM1->RCR = 0x0000;

TIM1->CCER = TIM_CCER_CC1E;

TIM1->CCMR1 = TIM_CCMR1_OC1FE | TIM_CCMR1_OC1PE | TIM_CCMR1_OC1M;

TIM1->BDTR = TIM_BDTR_MOE;

TIM1->DIER = TIM_DIER_CC1DE |TIM_DIER_UDE | TIM_DIER_TDE;

TIM1->CR1 = TIM_CR1_CEN;

Can somebody explain me how this configuration behave? Am I correct if I think the period of occuring events is (PSC+1)*(ACC+1)/72MHz ? (does the TIM1->CCR1 = (35+1)/2; have any meaning?) How works bits TDE and UDE?

I take a simple experiment with this configuration with set bits TDE UDE and without them but I dont see any difference (of course in DMA usage).

Tesla DeLorean · ‎2011-12-28

Posted on December 28, 2011 at 18:16

Pretty limited desire to decipher bit level TIM configurations.

The value of ARR suggests a frequency of about 64.516 KHz.

The computation for CCR1 suggests a desire for a 50/50 duty cycle.

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pawelcit · ‎2011-12-28

Posted on December 28, 2011 at 18:52

Thank You for reply. This configuration in general was created to trigger ADC by timer's events. Does the duty cycle (in this case 50%) have any effect to the frequency of events? What would be in case of ex. 10% duty cycle?

What do CC1DE, UDE and TDE bits do

practically

?