The output signals at the maximum frequency.

[scolonel]

Posted on December 21, 2011 at 12:45

How can I synchronize the timer output with a maximum frequency PLL,

ie 168 MHz.  In my example I set the timer to slow generate an interrupt, which run fast timer for generating a single pulse duration of 6 ns, but I have a jitter of 10 ns. Example my codes: 1)   /* Time base configuration TIM9 (fast)*/   TIM_TimeBaseStructure.TIM_Period = 100;   TIM_TimeBaseStructure.TIM_Prescaler = 0; // max freq. (168 MHz)   TIM_TimeBaseStructure.TIM_ClockDivision = 0;   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;     TIM_TimeBaseInit(TIM9, &TIM_TimeBaseStructure);     /* TIM9 PWM2 Mode configuration: Channel1 */   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;   TIM_OCInitStructure.TIM_Pulse = 100;//get pulse ~6ns   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;     TIM_OC1Init(TIM9, &TIM_OCInitStructure);     /* One Pulse Mode selection */   TIM_SelectOnePulseMode(TIM9, TIM_OPMode_Single);     /* Time base configuration TIM3 (slow) */     TIM_TimeBaseStructure.TIM_Period = 1000;   TIM_TimeBaseStructure.TIM_Prescaler = 8;   TIM_TimeBaseStructure.TIM_ClockDivision = 0;   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;     TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);     /* PWM1 Mode configuration: Channel4 */   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;   TIM_OCInitStructure.TIM_Pulse = 0; // pulse for control   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;     TIM_OC4Init(TIM3, &TIM_OCInitStructure);     //TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Enable);     TIM_ARRPreloadConfig(TIM3, ENABLE);   /* TIM Interrupts enable */   TIM_ITConfig(TIM3, TIM_IT_CC4 , ENABLE);     /* TIM3 enable counter */   TIM_Cmd(TIM3, ENABLE);    2) config output pins    /* TIM3 clock enable */   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);     /* Enable peripheral clocks */   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOE, ENABLE);   /* TIM9 clock enable */   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);   /* TIM3_CH4 pin (PC.09) configuration */   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;   GPIO_Init(GPIOC, &GPIO_InitStructure);     /* TIM9_CH1 pin (PE.05) configuration */   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;   GPIO_Init(GPIOE, &GPIO_InitStructure);   3) interrupt config   /* Enable the TIM3 gloabal Interrupt */   NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;   NVIC_Init(&NVIC_InitStructure);   4) interrupt routine void TIM3_IRQHandler(void) {   if (TIM3->SR & TIM_IT_CC4) //   {     /* Clear the IT pending Bit */     TIM3->SR &= ~TIM_IT_CC4;     TIM9->CR1 |= TIM_CR1_CEN; // start new pulse   } }   TIM9_CH1 (PE.05) output should be synchronized with TIM3_CH4 (PC.09) oputput, but it don't. How to fix this trouble? #stm32f4-discovery

[Tesla DeLorean]

Posted on December 21, 2011 at 17:39

The values for Prescale and Period take the form (N - 1)

For 1000 cycles, use 999 Pulse of 0 is always OFF, 1000 is always ON Period = 100 - 1; // 100 cycles Pulse = 99; // Low for a single tick, High for 99 (out of 100)

[scolonel]

Posted on December 21, 2011 at 18:09

Thanks! B

ut

I installed the

other

pulse durations

, the jitter

is still

present.

[Tesla DeLorean]

Posted on December 21, 2011 at 20:10

If it is jitter, then I'd start by using clock sharing a common divider source (ie APB2) and the same prescaler.

A jitter of ~6ns suggests its falling on either side of an odd divider (asymmetrical duty cycle)