System Clocks for both cores are not correctly set (NUCLEO-H755ZI-Q board)

[binarybee]

Hi guys, I recently posted similar question but now I have some actual measurements.

I have measured the frequency of the clock signal comming from st link to microcontroller which was 8 MHz (correct). Then I did setup of prescalers, configure system clocks source etc. The code is following for the 480MHz setup of CPU1 and 240MHz for CPU2.

    MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), PWR_CR3_LDOEN);
    MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1));
    SET_BIT(RCC->CR, RCC_CR_HSEBYP);
    SET_BIT(RCC->CR, RCC_CR_HSEON);
    while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != (RCC_CR_HSERDY));
    MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, RCC_PLLCKSELR_PLLSRC_HSE);
    SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
    SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (uint32_t)(0x00000003) << RCC_PLLCFGR_PLL1RGE_Pos);
    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (uint32_t)(0x00000000U)  << RCC_PLLCFGR_PLL1VCOSEL_Pos);
    MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, 1 << RCC_PLLCKSELR_DIVM1_Pos);
    MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (120-1UL) << RCC_PLL1DIVR_N1_Pos);
    MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (2-1UL) << RCC_PLL1DIVR_P1_Pos);
    MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (20-1UL) << RCC_PLL1DIVR_Q1_Pos);
    MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (2-1UL) << RCC_PLL1DIVR_R1_Pos);
    SET_BIT(RCC->CR, RCC_CR_PLL1ON);
    while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != (RCC_CR_PLL1RDY));
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_D1CFGR_HPRE_DIV2);
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL1);
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_D1CFGR_D1CPRE_DIV1);
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_D1CFGR_HPRE_DIV2);
    MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, RCC_D2CFGR_D2PPRE1_DIV2);
    MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, RCC_D2CFGR_D2PPRE2_DIV2);
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_D1CFGR_D1PPRE_DIV2);
    MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, RCC_D3CFGR_D3PPRE_DIV2);

After disabling interrupts I did measurement with oscilloscope by triggering pin in main loop ( high and low ), with some counter values to not have on ouptut 480MHz. The frequency of the CPU1 was around 1.38MHz. Then I also did the same think for systick and frequency matched the core one (1.38MHz). Is this even possible to get such a low frequency from the system?

Thanks a lot for every answer and advice!

[TDK]

It's certainly possible to set the system clock as low as that.

However, toggling a pin in a main loop is not a good way to measure the clock. Each toggle will take more than one instruction cycle in general, and the loop back part will also take a cycle, or more.

A better technique would be to enable MCO and measure that frequency.

[binarybee]

I know that using main loop is not the best solution, but it shouldnt be 1.38MHz, because this is for sure not caused by few instructions and memory delays. Besides that, I dont really know what can cause this state of CPU clocks. Looks like timer (TIM1) has the correct frequency. There are no other settings or configurations, just system init, after that clocks configuration, and then main loop. I dont really know what can cause this (maybe some incorrect pwr source configuration or even if is some jumper configuration on board not correctly configured). I checked the manual for the board but it seems like everything is prepared for the bypass of X2 with stlink clocks. If anybody has some hints or dealt with the same problem before please contact me. I tried multiple configurations,I used also stm IDE and cubeMX without any success.

Thanks!

[TDK]

> If anybody has some hints

Stop using an arbitrary measurement to measure the system clock speed.

Examine the RCC registers.