Synchronizing code with ADCCLK in STM32F746

[RBack.1]

My goal is to start ADC conversions a deterministic amount of time after raising a GPIO.

Since the ADC clock is slower than the instruction clock, the instruction to set SWSTART can occur in between ADC clock cycles. I currently have the ADC clock set to fPCLK2/2 and PCLK to HCLK/2, so I see up to 3 instruction cycles of jitter between raising the GPIO and starting the samples. Is there a technique useful for eliminating this jitter?

[TDK]

One possibility would be to use a timer to trigger the ADC and use the same timer to generate the GPIO edge. If the timer runs at the ADC speed, it should be consistent.

[RBack.1]

Thank you for your reply. I will investigate this option.

I will need to use the interrupt for the timer? Just checking flags introduces jitter. Unfortunately the hardware I have inherited does not use a pin that is attached to a timer. The ISR needs to be in ITCM as well?

[TDK]

Don’t use an interrupt. Use a channel of the timer in PWM mode to generate the rising edge deterministically with respect to the adc clock.

[waclawek.jan]

> Unfortunately the hardware I have inherited does not use a pin that is attached to a timer.

Namely?

JW

[RBack.1]

The GPIO pin on the hardware I inherited is not connected to a timer, however. It seems the best I can do is use an interrupt, raise the pin with an instruction, and then start the adc deterministically wrt the timer that caused the interrupt?

[RBack.1]

The hardware was designed by a contractor who I have replaced. The company owns a lot of these boards, however, and I need to do the best I can with what I have.

[waclawek.jan]

No, I mean, which pin exactly is the one you want to output the sync onto.

JW

[RBack.1]

There are several pins. PB0-2, PE2-4, and PE9-PE14.

[TDK]

So 12 different pins? You want them all to have the same signal? Or are you trying to sync different pins with different ADC channels being sampled?