STM32U5A5 Hard fault setting SYSCLK > 64Mhz

[moylando]

I'm trying to crank up the clock to Timer1 to be able to count high frequency events with better resolution.  If I set the SYSCLK to 128 I get a hard fault when my code reaches SystemClock_Config().  Even if I keep the AHB bus at the same speed (64Mhz) using prescaler.  In this case the only clock difference seems to be SYSCLK value.

Here's the first configuration which works ok:

and here's the other where it will hard fault:

Since the IDE says I should be able to take HCLK to 160Mhz which would require a much higher SYSCLK, I don't see why this SYSCLK value should cause a fault.

[moylando]

No, doesn't work.  Any setting with SYSCLK > 112Mhz does not work.  I've tried 160Mhz with multiple AHB prescalers (not even upping the AHB frequency later, so AHB stays lower) and it seems totally insensitive.  The only factor I've been able to deduce is the SYSCLK setting.

[moylando]

I added this block between enabling the PLL and updating RCC clock config (which are both done in the code generated by CubeIDE).  I did this because I noticed in the registers that the BOOSTRDY flag was not set:

    uint32_t timeout;
    timeout = ((0x64U * (SystemCoreClock / 1000U)) / 1000U) + 1U;
    while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_BOOSTRDY) && (timeout != 0U))
    {
      timeout--;
    }

    if (timeout == 0U)
    {
      Error_Handler();
    }

This did manage to wait correctly for the flag to be set before proceeding, but unfortunately made no difference at SYSCLK = 128Mhz.

[Tesla DeLorean]

Power Supply, lack of adequate bulk capacitance on the supply side, or at VCAP pin(s)

Flash Wait States / Latency

Caching or Prefetch settings

[moylando]

Changed this auto generated code:

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  {
    Error_Handler();
  }

from LATENCY_1 to LATENCY_2 and it's now running at SYSCLK=128 / HCLK = 64

According to this doc:

https://www.st.com/content/ccc/resource/training/technical/product_training/group1/95/d2/99/8c/32/75/40/6b/STM32U5-Memory-FLASH_FLASH/files/STM32U5-Memory-FLASH_FLASH.pdf/_jcr_content/translations/en.STM32U5-Memory-FLASH_FLASH.pdf  Page 7  it should be OK with LATENCY_1 upto 64Mhz.

Not sure why that won't work.  Will keep experimenting with increasing clock frequency.

[Tesla DeLorean]

Other STM32 the FLASH max clock is ~27 MHz (or around 35ns), but can be quite wide

LATENCY_2 is basically 3-cycle memory

Speed of FLASH also a function of Voltage, slower at low voltages

[moylando]

Best I've been able to manage is SYSCLK = 136Mhz, HCLK = 34Mhz, waiting for BOOSTRDY before updating the ClockConfig, then stepping up HCLK to 68Mhz.

Can't get SYSCLK past that, even leaving HCLK with /4 prescale.  And can't get HCLK to 136Mhz even doing a further wait and step.

Are hardware based issues, as in voltage or capacitance issues often found on Nucleo boards?  

[moylando]

Hmm, page 27 of this Nucleo doc says HSE is 16Mhz.  But my CubeIDE project seemed to initialize HSE to 8Mhz.  Have I just been doing experiments in overclocking?  I'll confirm with a scope in the morning.

[Tesla DeLorean]

Are you using a NUCLEO board, or a custom one?

Might depend what solder-bridges are made, and if jumpered to lower voltage options.

[AScha.3 · Accepted solution]

Board should have 16M crystal:

So your sysclock "136M" setting is 272 MHz , a bit too much for 160MHz cpu. :)

Set your clocktree with 16M HSE, and sysclk 160M , AHB div. 1 , so AHB also 160M.

[moylando]

An elegant and simple solution. :')  Still curious why the auto-generated code doesn't seem to follow any of the guidelines on maximum clock Hz step and BOOSTRDY flag, but that's for another day.

Thanks, all.