2024-04-15 03:09 AM
Hi, this is new for me. im working with a project that includes an STM32U575RIT6Q controlling a device through the SPI3 interface at 40MHz with 8 bits per word, SPI mode 0, and the GPIO change speed at very high. The microcontroller is running at 160MHz using PLL with the HSE.
The issue here pops up when i call the function HAL_SPI_Transmit or HAL_SPI_TransmitReceive with a bytes length of 1024 bytes or longer. The SPI transaction fails because the bit named
#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
could not reset to 0.
This issue is not happening when the bytes lenght of the transaction is shorter than 1024 bytes. here is the code im using for this test.
void MX_SPI3_Init(void)
{
/* USER CODE BEGIN SPI3_Init 0 */
/* USER CODE END SPI3_Init 0 */
SPI_AutonomousModeConfTypeDef HAL_SPI_AutonomousMode_Cfg_Struct = {0};
/* USER CODE BEGIN SPI3_Init 1 */
/* USER CODE END SPI3_Init 1 */
hspi3.Instance = SPI3;
hspi3.Init.Mode = SPI_MODE_MASTER;
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
hspi3.Init.DataSize = SPI_DATASIZE_8BIT;
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi3.Init.NSS = SPI_NSS_SOFT;
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi3.Init.CRCPolynomial = 0x7;
hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
hspi3.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
hspi3.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
hspi3.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
hspi3.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
hspi3.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
hspi3.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
hspi3.Init.IOSwap = SPI_IO_SWAP_DISABLE;
hspi3.Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY;
hspi3.Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH;
if (HAL_SPI_Init(&hspi3) != HAL_OK)
{
Error_Handler();
}
HAL_SPI_AutonomousMode_Cfg_Struct.TriggerState = SPI_AUTO_MODE_DISABLE;
HAL_SPI_AutonomousMode_Cfg_Struct.TriggerSelection = SPI_GRP2_LPDMA_CH0_TCF_TRG;
HAL_SPI_AutonomousMode_Cfg_Struct.TriggerPolarity = SPI_TRIG_POLARITY_RISING;
if (HAL_SPIEx_SetConfigAutonomousMode(&hspi3, &HAL_SPI_AutonomousMode_Cfg_Struct) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI3_Init 2 */
/* USER CODE END SPI3_Init 2 */
}
for(;;)
{
if( prueba == 0 )
{
printf("Error SPI with 1024 bytes %u.\n", HAL_SPI_Transmit(eps_intf.spi3, dataWrite, 1024, 1000) );
printf("Error SPI with 1023 bytes %u.\n", HAL_SPI_Transmit(eps_intf.spi3, dataWrite, 1023, 1000) );
osDelay(5000);
}
}
This is the output:
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Error SPI with 1024 bytes 1.
Error SPI with 1023 bytes 0.
Where the 1 means HAL_ERROR and the 0 means HAL_OK. I dont know is this behavior is related to the version of the CubeIDE(1.15.0), the version of the HAL libraries or the Cortex-M33. I have tested this same transactions with an STM32L452RET6 and no error were present.
Solved! Go to Solution.
2024-04-16 08:35 AM
Hello @cesarv
The SPI3 integrated into the STM32U5 is a limited-feature instance with 10-bit data counter (TSIZE [9:0]). The maximum value to be stored at this bit field is 0x3FF ~ 1023.
I checked your configuration and noticed that the NSSPMode is enabled (which should activate the SSOM bit) but MasterInterDataIdleness is set to 0. I suggest keeping the NSS output activate (SSOE =1) and not apply NSS pulses between data (which occur at case MIDI bitfield is set >1).
For more details, please refer to the section "68.4.7 Slave select (SS) pin management" in RM0456.
kind regards,
Nissrine.
2024-04-16 08:35 AM
Hello @cesarv
The SPI3 integrated into the STM32U5 is a limited-feature instance with 10-bit data counter (TSIZE [9:0]). The maximum value to be stored at this bit field is 0x3FF ~ 1023.
I checked your configuration and noticed that the NSSPMode is enabled (which should activate the SSOM bit) but MasterInterDataIdleness is set to 0. I suggest keeping the NSS output activate (SSOE =1) and not apply NSS pulses between data (which occur at case MIDI bitfield is set >1).
For more details, please refer to the section "68.4.7 Slave select (SS) pin management" in RM0456.
kind regards,
Nissrine.