STM32U5 Regular Command vs HyperBus protocol

[dboles42]

I'm looking for some more information when it comes to the STM32 OctoSPI support for Regular command versus HyperBus protocols when it comes to interfacing with an external PSRAM in Memory Mapped mode.

We are considering a ISSI OctaRAM part vs HyperRAM due to the operating temperature of 125C for the OctaRAM variant vs 105C for all the HyperRAM variants. We will also have external QuadSPI flash that will not be HyperFlash compatible.

We want to do some risk reduction by getting the the U5 IOT dev board that has an external OctoSPI memory onboard, but am worried that since it's a "HyperRAM" variant that whatever proof of concept we run isn't going to be 1-to-1 when we get our prototypes with the OctaRAM part.

I have a few questions:

• Can we operate the “HyperRAM�? part in “Regula�? command mode since the DQS pin is optional in Regular Command mode?
• If not, is there anything we should consider when it comes to the U5 OctoSPI peripheral support when it comes to using external memories in memory mapped mode w/ the Regular Command protocol?
• Is there any limitation to interfacing with the quadSPI flash while running the OctaRAM in memory mapped mode?

Thanks!

[ChahinezC · Accepted solution]

Hello @Community member​,

• When using HyperRam, it is mandatory to use the HyperBus protocol.
• The DQS signal can be used for data strobing during the read transactions when the device is toggling the DQS aligned with the data, so it is not only required for the HyperBus protocol but can also be enabled when using the regular-command protocol when supported by the memory.
• Quad-SPI flashs and Octo-SPI rams are supported in STM32U5 products, for any OCTOSPI limitations I recommend you referring to the product's erratasheet ES0499.

I hope my answer helped you; please mark it as best by clicking on the "Select as Best" button if it fully answered your question.

Chahinez.

[dboles42]

Thank you for the info, this helps.

I ended up settling on a HyperRAM due to part availability at least for our first spin, so the question was mostly moot, but the errata document is very helpful.