STM32U0 timer clocks x2

[Hans_W]

In contrast to the STM32L0 that I am migrating from to the newer STM32U083, the U0 clock tree (Reference manual RM0503 V2.0 figure 11) does NOT show that timer clocks are PCLK*2 when APB prescaler>1.

Also, it states in 5.2.14 that timer clock TIMPCLK is equal to PCLK. In other STM32 series like F1, L4 and L0 I was used to have timer clock doubling when PCLK<HCLK. A feature I always disliked, because it requires reconfiguring timers when you want to throttle the CPU speed.

However:

• The HAL (STM32Cube_FW_U0_V1.2.0) function HAL_RCCEx_GetPeriphCLKFreq() returns 2x PCLK, but only for TIM15 and TIM1 in that case (APB prescaler>1). This exception for TIM1 and TIM15 is nowhere to be found in the reference manual.
• When I configure TIM6 to clock from 8MHz PCLK (1/2 of my 16MHz HCLK) with prescaler 8 (PSC register value 7) it appears to run twice as fast as expected: 2MHz instead of the expected 1MHz. Apparently it is clocked bt 16MHz (2*PCLK). 
  (in contrast, my UARTs run at the expected 8MHz clock, as the baud rates are correct)

Can someone tell me (and afterwards upate the Reference Manual of STM32U0) for which timers the PCLK is doubled (like in other STM32 series) when the APB prescaler is larger than 1? Or is this a silicon bug and wasn't this supposed to happen?

Maybe the firmware library (hal_rcc/hal_rcc_ex) needs an update as well, if the U0 behaves like L0/L4/F1 in this case.

[Bubbles]

Hi @Hans_W ,

no it's only TIM1 and TIM15 that use the TIMPCLK. Another way to look at the timer clock options is to see the RCC_CCIPR settings. It lists all the options available and their values.

The TIMPCLK is inherited from STM32G0, where the multiplier was a trick to overclock the timer to reach 128MHz - great for PWM. But that was not efficient enough for the ultra low power U0 and the option for x2 clock was to be removed. A miscommunication led the design to only remove the multiplier from the undivided clock, while the RM master original intention was to remove it completely.

BR,

J

[Hans_W]

Hi Bubbles,

As you can see in your own highlighted signal, TIMPCLK is also routed to the right, towards TIM2/3/6/7/16, but the placement of the TIMPLCK name is ambiguous, as if it only goes left, to TIM1/TIM15. 

The RM is missing the exact point where PCLK is doubled to TIMPCLK in case APB PRESC>1, It seems to work like this (explaining why TIM6 runs at 2xPCLK, which is why I started this topic):

By the way, it isn't as new a feature, the good old STM32F1 series behaved the same, doubling PCLK1 and PCLK2 for timers only, so I was surprised at first that STM32U0 wouldn't have this PCLK doubling.

If the above picture is correct, that would also indicate that the LPTIMx timers run on regular PCLK.

[Hans_W]

To resume:

• clock tree (Fig 11) should be corrected to include the x2 step in case PCLK PRESC >1
• 5.2.14 should be clarified that TIMPCLK is 2x PCLK frequency if PCLK PRESC >1 and that it is fed to all TIMx, but not to LPTIMx.

[Bubbles]

@Hans_W ,

yes, that's the change we need to do in the next RM revision. But we won't use the exact phrase "all but LPTIM". I'd rather be specific and say it's for TIM1 and TIM15.

BR,

J

[Hans_W]

Hi Bubbles,

Please look again, it is not limited to TIM1/TIM15, TIMPCLK is fed to all TIMx, including TIM2/3/6/7/16, see the yellow highlighting in my picture above. Make sure the point where the "X2" is performed is on the right spot in the signal lines.

Otherwise TIM6 would never have been running at the double PCLK frequency, as observed. 

If you look at the CubeMX clock diagram you see the same TIMPCLK signal, slightly renamed to TPCLK, being fed to TIM1/TIM15 but also being output as "APB Timer Clocks" (my post of Feb 18).

So you can phrase it in 5.2.14 as "TIMPCLK is used for all TIMx timers. The LPTIMx timers use regular PCLK when selecting the peripheral clock"

[waclawek.jan]

If it's exactly the same scheme as in 'L0 - and it appears to be so from the conversation above - why don't you just use the same phrasing and same depiction as in 'L0 RMs?

JW

[Hans_W]

You're almost right: TIMx and LPTIMx clocking seems identical to L0, but STM32U0 also has TIM1/TIM15 with the additional PLLQCLK option. The only thing missing is the "X2" step in the clock tree and in 5.2.14. The L0 RM doesn't have that paragraph.