About Hans_W

Hans_W · 2025-02-17

In contrast to the STM32L0 that I am migrating from to the newer STM32U083, the U0 clock tree (Reference manual RM0503 V2.0 figure 11) does NOT show that timer clocks are PCLK*2 when APB prescaler>1.Also, it states in 5.2.14 that timer clock TIMPCLK ...

Hans_W · 2025-02-10

I'm trying to find out the exact steps to regress an STM32U083 to an erased state after programming it with the OEMiRoT example project and and locking it to RDP2 by the accompanying provisioning.bat script.Will be using STM32CubeProgrammerCLI (or th...

Hans_W · 2024-11-11

The OEMiRoT project uses ExitSecureMemory V1.1 to enable 1 MPU region and start the application. This automatically enables the configured HDP region, so application cannot access the bootloader. The default OEMiRoT project allows for 2 tiny 64kB app...

Hans_W · 2024-09-16

I'm aiming to use the OEMiRoT sample project as a concept for secure updating of a large single-slot application in STM32U083 (need application size at least 160kB for migration from STM32L071). For that I need to give the bootloader a driver for ext...

Hans_W · 2024-08-14

I'm planning to drop in an STM32L083RC into a design made for STM32L071/073/083RZ (LQFP64) and was confident after reading AN6091 that apart from USBVDD it would be pincompatible.It appears I cheered too soon, after I dived into the U083 datasheet an...

Hans_W · 2025-02-21

You're almost right: TIMx and LPTIMx clocking seems identical to L0, but STM32U0 also has TIM1/TIM15 with the additional PLLQCLK option. The only thing missing is the "X2" step in the clock tree and in 5.2.14. The L0 RM doesn't have that paragraph.

Hans_W · 2025-02-21

Hi Bubbles,Please look again, it is not limited to TIM1/TIM15, TIMPCLK is fed to all TIMx, including TIM2/3/6/7/16, see the yellow highlighting in my picture above. Make sure the point where the "X2" is performed is on the right spot in the signal li...

Hans_W · 2025-02-20

To resume:clock tree (Fig 11) should be corrected to include the x2 step in case PCLK PRESC >15.2.14 should be clarified that TIMPCLK is 2x PCLK frequency if PCLK PRESC >1 and that it is fed to all TIMx, but not to LPTIMx.

Hans_W · 2025-02-20

Hi Bubbles,As you can see in your own highlighted signal, TIMPCLK is also routed to the right, towards TIM2/3/6/7/16, but the placement of the TIMPLCK name is ambiguous, as if it only goes left, to TIM1/TIM15. The RM is missing the exact point where ...

Hans_W · 2025-02-19

Hi Bubbles, I didn't doubt CubeMX's TPCLK branch and I certainly don't feel mislead, but the diagram doesn't explicitly cover all existing timers and the LPTIMx timers seem not to use TPCLK but PCLK instead.So, did this RCC design lead confirm my gue...

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STM32U0 timer clocks x2

STM32U0 OEMiRoT RDP regression appnote?

ExitSecureMemory MPU region limitation (OEMiRoT)

debug OEMiRoT-Boot project on U083 possible?

STM32L07x to STM32U083 migration and pincompatibility (AN6091)

Re: STM32U0 timer clocks x2

Re: STM32U0 timer clocks x2

Re: STM32U0 timer clocks x2

Re: STM32U0 timer clocks x2

Re: STM32U0 timer clocks x2