STM32L4S PLL accuracy with the HSE clock

[SChen.7]

I want to feed the HSE clock (sourced by a 4MHz oscillator) to the PLL to create a SYSCLK at a higher frequency. Is there accuracy information on the PLL or is the accuracy of the output clock driven by the external oscillator? I've checked the data sheet with no luck but I may have missed something.

Thank you.

[Tesla DeLorean]

ST really hasn't characterized these things in my experience. A couple of the parts they've suggested viable range of the internal comparison frequency and VCO.

You might want to push this query into a local sales office or FAE, or submit via an "Online Support" ticket.

[waclawek.jan]

This probably depends on exact definition of what "accuracy" might mean, but IMO generally, accuracy of PLL is given primarily by accuracy of the driving clock, i.e. here the crystal oscillator or external oscillator used.

Jitter is another thing. It is *somehow* characterized in the DS:

JW