STM32L4R7ZIT exiting / returning from STOP1

[NArnd]

Hello,

I'm trying to understand which steps need to be taken when exiting the stop modes with STM32L4R7ZIT.

Say that we are in stop1 mode, RCC->CFGR-STOPWUCK == 0 (MSI).

Before entering stop1 we were clocked by HSE 12 MHz via the main PLL into 120 MHz SYSCLK (range 1 with boost).

When exiting / returning from stop1 this is what we want to restore.

RM0432 v8 table 26 has two columns for "Voltage regulators"; MR (main) and LPR (low-power).

However, RM0432 v8 5.4.1 says "the regulator is switched from ... MR to ... LPR" and 5.4.6 says "The regulator".

But 5.1.6 says "Two embedded linear voltage regulators".

* Is it one voltage regulator with e.g. two different feedback resistor configurations that are switched by a transistor?

* Or is it two separate voltage regulators that are individually enabled / disabled and is there some circuitry to connect none or one of them to the supply rail?

The practical question is how many SW configuration points there are and which of them are automatic and which of them must be manually set.

Maybe the electronic design could provide an answer?

E.g. PWR->CR1-LPR resets to 0 (MR) and setting this bit to 1 enables low-power run. (Supposedly you must first set SYSCLK to <= 2 MHz.)

* Is this the bit that controls which voltage regulators (MR and/or LPR) are ON in accordance with table 26?

* If this is the case, is this bit set automatically when entering stop1, stop2, standby, and shutdown?

* If this is the case, is this bit cleared automatically when exiting stop1 and stop2? (Exiting standby and shutdown cause a power reset.)

Related to this:

* Does the PWR->CR1-VOS == 10 Range 2, referred to as "Low-power range" (RM0432 v8 p190), have any direct relation to the voltage regulator low-power mode (LPR)?

* Or, does the PWR->CR1-LPR == 1 low-power mode (LPR) work regardless of PWR->CR1-VOS range so long as SYSCLK is <= 2 MHz?

Also related:

The Nucleo L4R5ZI stop1 example is based on 4 MHz MSI via PLL into 120 MHz.

The initial SystemClock_Config sets it to range 1 with boost and first divides AHB by 2 and then goes to AHB /1.

This is in accordance with RM requirements.

However, the example's SYSCLKConfig_STOP() function (that is called when exiting / returning from stop1) doesn't go via AHB / 2.

Apart from this potential bug, is exiting stop1 only a question of re-enabling PWR_CLK and PLLs, and re-selecting PLL as source for SYSCLK?

Shouldn't you first do

PWR->CR1 = PWR->CR1 & (~LPR); // Switch from regulator low-power mode (LPR) to main mode (MR)

while ((PWR->SR2 & PWR_SR2_REGLPF) != 0U) {} // Wait until the regulator is ready in main mode (MR)

?

Best regards

Niclas