Posted on October 06, 2017 at 19:56No doubt, this was more of an intellectual exercise to see how much headroom there was in the design. Figuring more advantageous design than the original F2/F4, better process, and peripheral buses now running at 100-108 MHz in some of the designs.
The Cortex-M0(+) parts can also run faster than advertised, but with limited flash wait state options, pll settings, and no cache/prefetch as speed ramps above 28 MHz the speed of the flash becomes dominant.
