STM32L4 OTG_FS_VBUS issues again

[dimitri]

Posted on September 01, 2015 at 22:23

I am planning to use STM32L4 on a device powered by two alkaline batteries, and I'd like to use USB OTG. After reading the docs, i have came across a few problems:

The first problem is the limitation regarding the 5V tolerance on VBUS (PA9). This is the problem described in 

/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/STM32F105%20PA9OTG_FS_VBUS%20Issues&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=1796

 (but the thread deviates to another problem related to the bootloader). Basically, the PINs are 5V tolerant only when power is applied to the chip. In my case, if the USB plug is attached to a device that contains no batteries, 5V will be applied to PA9 while no power is provided to the chip (until the external USB regulator that takes over the batteries starts, but it takes a few ms). The first idea is using a resistor between VBUS and PA9, but if we use USB OTG with SRP, is it still relevant ? The USB PHY charges and discharges VBUS through PA9, right ? So a high value resistor would defeat this purpose. I tried to imagine a simple way using a mosfet driven only when the chip is powered, but it is not that easy, since current can flow both ways and VBUS can go down to 0V. Commerically available analog switches also limit the input voltages to the supply voltages, so the problem remains. Is there a simple solution ?The second problem is when the device acts as a USB A-device. VDD is provided from two batteries (so from ~1.8V to  ~3.0V). I plan to power only VDDUSB through a tiny boost regulator (at 3.3V) to make the design as efficient as possible. Then I came across the errata and problem 2.1.3 (Some I/Os must not be used as output when VDDUSB > VDD + 0.6 V). Does the usage of PA9 as OTG_FS_VBUS count as an output ? Does it fall into this limitation ? What magnitude is the leakage ? In this case, is powering the whole chip at 3.3V when I use USB OTG the only solution ? I saw this is fixed for silicon rev 4, but I don't know yet which revision my sample chips will be.An additional question: what is the consumption on VDDUSB ? I saw on the datasheet that the OTG_FS consumes 23.2µA/MHz (independant clock domain) + 16.4µA/MHz (AHB), but is it through VDD or VDDUSB ?Thanks null

[dimitri]

Posted on September 02, 2015 at 22:30

Regarding the first problem, here is what I came up with. I must say I am quite proud of it...

When VBUS > VDD + ~3.6V, the zener triggers to the NPN which shuts the MOSFET off (this is a depletion MOSFET). This results in the PA9 PIN being kept at the threshold voltage of the MOSFET (max 3.5V) until the voltage difference between VDD and VBUS goes back to a safe level. At normal operation, this circuit leaks 1µA only through the zener, and the only other consequence is the Rds(on), so about 4 ohm, between VBUS and PA9. But I can't help thinking that it is overengineered, since that problem is certainly quite common, as it can easily happen on both bus-powered devices (during the time the regulator turns on), and self-powered devices (when it is shut down). Am I missing something ? EDIT: Except that if VDD > VBUS (batteries but no USB cable plugged), VDD seriously leaks through the 12k resistor. So instead of the 12k resistor, we need a lower value (like 5.6k) and a schottky with low leakage (BAS40 or something) with the cathode towards VDD... I told you this was overengineered...