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STM32L4 ADC oversampling - What is the total sampling time ?

KK.4
Associate II

I using STM32L4 ADC in my project to sample analog acceleration data. The ADC conversion is triggered by 10kHz timer by which i was able to achieve 10kHz sampling rate using DMA.

Now, i wanted to implement oversampling by a factor of 2. Now what is my sampling frequency?

Is each sample still collected at 10kHz and averaged to reach 5kHz? Meaning if want to collect 100 data samples (DMA complete callback), would the total sampling period to complete 100 acquisitions, increased by the oversampling factor of 2?

Example: 

With 10kHz, 100 points

Total sampling time = (100/10k) = 0.01 seconds (Time taken for DMA complete callback to trigger)

With oversampling of 2,

Total sampling time = (100/5k) = 0.02 seconds (Time taken for DMA complete callback to trigger)

Is my understanding correct?

3 REPLIES 3
AScha.3
Chief

most - do not be confused by the word oversampling .

as long as you dont use a digital filter, it is just the average of n sampels.

so you collect 100 points in time at 10kHz, sum -> you get one sample in 10ms or at 100Hz , but with better resolution (lower noise and rect. time window with sinx/x filter effect - but probably not important here).

so if ADC summing 4 sampels (oversampling mode) and you sum 50 of these, or you sum 200 sampels (12bit "original" data with same timing) is the same result; just the time the cpu uses to collect the data is different and so you can optimize the used cpu time to get the desired resolution.

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Thanks for your quick response.

I am using anti-aliasing filter before the ADC. I wanted to have fixed sampling frequency to have fixed cut-off anti-aliasing filter (to respect the Nyquist criteria). But my application demands to have variable sampling frequencies depending on the deploying machine's rotating speed (Have to capture data for fixed number of rotations , say 10 rotations )

I am not looking to improve the resolution of ADC by oversampling but

  1. To relax the anti-aliasing filter constrains before the ADC
  2. Increase or decrease the total sampling time of the ADC by oversampling factor, without increasing the number of data points and actual sampling frequency. (If i increase or decrease the ADC sampling frequency, i have to change the analog filter design to respect the new Nyquist criteria)

Considering 10Khz trigger to ADC

Time taken by oversampling ADC(by factor 4) to collect 100 data points = Time taken by normal ADC to collect 400 data points ? Is my understanding correct?

yes , if adc keeps constant timing always; if adc on oversampling captures with high speed the 4 sampels to get the result in samping intervall you set , no.

i dont know - just read in rm of your chip, what timing is used, when you set oversampling mode. i read on H743 rm , >There are no changes for conversion timings in oversampled mode: < so you get always the same sampling rate, just the data you read is from one sample or the average of the last N sampels.

+

Increase or decrease of sampling time and filter cutoff when speed changes is not needed;

first decide, what is max. frequ. you need; (or max. you can use)

then make analog filter for this frequ. ; and set adc sampling to (Nyquist -> >2x ) lets say 3x this max. filter frequ. ;

now you get it the other way round: for 10 rotations now you get a data block with matching lenght; slow rotation -> more sampels, longer block.

but your data is always "correct" , filtered and no alias.

now if looking for a fixed relative move in the data, say a "10% window" , you have to calculate how long is 10% at this speed in your constant sample frequ. data and you can calculate same....

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