Hi
In the STM32L081 datasheet (DS10888 Rev 6: https://www.st.com/resource/en/datasheet/stm32l081cz.pdf ), on page 16, under "3.1 Low-power modes" there is this note:
CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5 μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
In the example given:
fcpu initial = 4.2MHz
fcpu final = 32 MHz
which gives true for:
4.2 MHz < 4*32 MHz
And also 4.2 MHz < 4*16 MHz, 16 MHz < 4*32 MHz... so it doesn't make sense.
Is this an erratum, and should be fixed in the pdf, or do I not understand how this inequality statement works?
Shouldn't this be:
CPU frequency changes from initial to final must respect "fcpu final < 4*fcpu initial". It must also respect 5 μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
Because then 32 MHz < 4*4.2 MHz is not satisfied, but 16 MHz < 4*4.2 MHz and 32 MHz < 4*16 MHz would be.
It's < and not <=, so switching from 4 MHz to 16 MHz is not allowed, right?
(I know that it doesn't really matter, because < and <= is essentially the same in the physical world, it's never exactly 4 or 16 MHz, it might be 15.9999 or 16.0001... I'm just wondering how close to 4.0*f can it be)
