STM32G474, USB, and CRS not working in concert

[MSing.1713]

Greetings,

We have implemented a USB peripheral on the STM32G474RE discovery board using code that runs properly on the STM32WB and STM32F0 parts.  On the G474, the USB setup completes, but the USB bus quickly suspends after the completion of the configuration phase when the host receives descriptors.  We were able to fix this issue by disabling (not setting) the CRS_CR_CEN flag in the CRS module.  There are no samples of USB peripherals in the latest Cube release, so we don't have an easy way to share the running program.  We can setup HRTIM_PFC_TransitionMode which includes some USB code.

In 

./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c

 you will find this 

1561 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
 1562 {
 1563   uint32_t value;
 1564
 1565   /* Check the parameters */
 1566   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
 1567   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
 1568   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
 1569   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
 1570   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
 1571   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
 1572
 1573   /* CONFIGURATION */
 1574
 1575   /* Before configuration, reset CRS registers to their default values*/
 1576   __HAL_RCC_CRS_FORCE_RESET();
 1577   __HAL_RCC_CRS_RELEASE_RESET();
 1578
 1579   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
 1580   /* Set the SYNCSRC[1:0] bits according to Source value */
 1581   /* Set the SYNCSPOL bit according to Polarity value */
 1582   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
 1583   /* Set the RELOAD[15:0] bits according to ReloadValue value */
 1584   value |= pInit->ReloadValue;
 1585   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
 1586   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
 1587   WRITE_REG(CRS->CFGR, value);
 1588
 1589   /* Adjust HSI48 oscillator smooth trimming */
 1590   /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
 1591   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
 1592
 1593   /* START AUTOMATIC SYNCHRONIZATION*/
 1594
 1595   /* Enable Automatic trimming & Frequency error counter */
 1596   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
 1597 }

and you can see on line1596 that CR_CEN is set.  So, we believe that this is the expected configuration of the CRS peripheral.  

What we also observe is that the system ROM code enables the CRS peripheral via the RCC, but it does not set this CR_CEN bit.

What would probably be most helpful would be to have some sample code added to the Cube for USB so we can verify how the CRS peripheral is suppose to be initialized.  It may also help to have some documentation added to the RM that explains how to setup CRS for synchronizing the HSI48 clock from USB SOF and from an LSE.

Cheers