STM32L0 ADC clock source and CubeMX

[Jim Kaz]

Posted on January 18, 2018 at 17:49

Hi everyone!  I'm using an L071CBTx and I'm trying to figure out how to change the ADCs clock source using CubeMX.  According to the reference manual, 'the ADC can be derived either from the APB clock or the HSI16 clock'.  I can't figure out how to change it to anything other than the HSI clock.  The Clock configuration page of CubeMX has the source always coming from the HSI RC with no way to change it (other than the divider).  I'm using version CubeMX 4.22.1 and framework 1.9.0

Since I couldn't figure it out in CubeMX, I figured I would go manipulate the code directly... and can't figure it out there either.  I referenced an L4 project I have, and the following code gets generated in the clock setup: 

PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2

| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC; PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; PeriphClkInit.PLLSAI1.PLLSAI1N = 12; PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2; PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4; PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4; PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK | RCC_PLLSAI1_ADC1CLK;

I then tried to look up matching (or similar) defines in my L0 framework and there was nothing that had ADC selection or source in the name.... So how exactly do you change the ADC clock to be from the APB clock?

Thanks!

[jz KN]

Posted on January 19, 2018 at 03:39

I'm using the same chip, and I have the same issue but I have get it work. You need to choose the HSE first in RCC like the pic below,and then you can change PLL using HSE. ADC's clock you can change with the code:

hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;

#define ADC_CLOCK_SYNC_PCLK_DIV1         ((uint32_t)ADC_CFGR2_CKMODE)    /*!< Synchronous clock mode divided by 1

                                                                               This configuration must be enabled only if PCLK has a 50%                                                                               duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock                                                                               must by 50% duty cycle)*/#define ADC_CLOCK_SYNC_PCLK_DIV2         ((uint32_t)ADC_CFGR2_CKMODE_0)  /*!< Synchronous clock mode divided by 2 */#define ADC_CLOCK_SYNC_PCLK_DIV4         ((uint32_t)ADC_CFGR2_CKMODE_1)  /*!< Synchronous clock mode divided by 4 */

[Vijay Panchal]

Posted on January 19, 2018 at 07:49

As shown below click on Configuration >> ADC

You will get adc configuration Options,

ADC Setting >> Clock Prescaler can be found.

[zubizeratta]

Posted on February 28, 2018 at 16:26

There is a difference between clock sources of the STM32f070x and STM32F030x ADCs . For STM32F070 series only option is asyncronous 14 Mhz clock (you can check from datasheet) but Cubemx still shows other options and this is so confusing,