Hi,
I am integrating the STM32H7S7L8H6H in a custom board. In the reference manual I found two settings which I am looking for clarification for:
1) SBS_PMCR has a AXISRAM_WS bit to enable a single wait state for the AXISRAM. I do not have ECC enabled so this bit determines whether or not a wait state is added for AXISRAM accesses. With the bit set the reference manual states: "One wait state added when accessing any AXISRAM with ECC = 0. In this case, refer to
the datasheet for maximum frequency." I cannot find any relevant maximum frequency in the datasheet (DS14359 Rev 2) but I would have thought the maximum frequency would apply to the situation where there was 0 wait state rather than 1?
2) PWR_CSR2 has XSPI_CAP1 and XSPI_CAP2 settings to enable or disable a capacitor in the XSPI ports. Again the datasheet is referenced but I cannot find any description of this setting there. Does anyone know the value of these capacitors, which XSPI pins they are applied to and whether they are present during both input/output operations or just input ones?
Thanks,
John.
