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STM32H7A3 OTP Read Failure with Flash Latency 0 WS

Paul Richards
Associate II

Hi,

Are there any restrictions on reading OTP when the Flash LATENCY is configured for 0 wait states, and the AXI clock frequency / VOS are within the required range allowed for such?

With an STM32H7A3 with SYSCLK configured to HSIDIV4 (i.e. 16 MHz), VOS=0, AXI Clock = AHB Clock = 16 MHz, Flash LATENCY = 0, code executes correctly from Flash. However when a 16-bit read is requested within the OTP address range (e.g. 0x08FFF000UL), the MCU jumps into never never land.

If Flash LATENCY is changed to 1, then the OTP read works as expected.

RM0455 nor the Errata describe any additional restrictions that those described for the Flash itself, i.e. RM055 Table 15.

TIA,

Paul

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