2023-10-19 06:25 PM
I am using NUCLEO-H753ZI (STM32H753ZITxLQFP144).
Using ADC1_IN3 Single-ended (PA6) and DMA (Mode:Circular),
I want to perform high-speed sampling. (1MSa/s or more)
Calculated: 3.125MSa/s = 50MHz / 4 * (1.5 + 6.5) (Supplement: clockPrescaler=4, 1.5Cycles, 6.5ADC clock cycles)
*The clock uses 50MHz of PLL2.
However, it seems that the speed is only around 500kSa/s.
Please advise if there are any possible causes or places where the settings may be incorrect.
Solved! Go to Solution.
2023-10-23 07:14 PM
Take a look at the reference manual at the 25.4.3 ADC clocks section to see how the ADC clock is derived. This is the clock figure for the V revision. The Y revision does not have this divisor.
To find out what hardware revision you have, you can read the REV_ID field from the device.
You can read this field with the HAL_GetREVID() function and adjust your ADC prescaler accordingly.
if (HAL_GetREVID() == REV_ID_V) {
// prescaler 2
} else {
// prescaler 4
}
CubeMX also has a setting you're supposed to set based on the revision. Not sure how this plays into code generation.
2023-10-20 07:00 AM
Probably your code can't keep up with the rate of data generation and/or your methods of calculating how long it takes are flawed (e.g. have too much overhead).
Show some code, show how you're arriving at the 500kSa/s value.
2023-10-22 06:01 PM
The settings are done according to the attached contents.
The sampling time is confirmed as follows.
1. Prepare a 100 point buffer
2. Hit GPIO
3.Start ADC
→ HAL_ADC_Start_DMA(&hadc1, &adc1_data, SIZE)
4.Callback function that occurs when ADC completes
→ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
*Hit GPIO here
*Estimate the sampling time from the time between GPIOs using an oscilloscope.
2023-10-22 07:08 PM - edited 2023-10-22 07:08 PM
You calculated duration includes a lot of overhead. There is setup in HAL_ADC_Start_DMA and it takes a bit for HAL_ADC_ConvCpltCallback to be called.
Perhaps change your calculation method to offset for this amount of overhead:
> 3.125MSa/s = 50MHz / 4 * (1.5 + 6.5)
I don't think this math checks out. 50e6/4/8 = 1.5625 Msps
Note that revision V devices have an additional /2 ADC clock scaling.
2023-10-23 06:01 PM - edited 2023-10-23 06:02 PM
Thank you for your advice. It's a big help.
When I actually measured it, it turned out as follows.
duration_1: 1303us
duration_2: 2575us
duration_2 - duration_1 = 1272us
sampling frequency
1 / 1.272us ≒ 786kSa/s
(Theoretical value: 50e6/4/8 = 1.5625 Msps)
The sampling frequency is almost half of the theoretical value.
I think this is probably related to the comment below that you pointed out last time.
comment
[Note that revision V devices have an additional /2 ADC clock scaling.]
I'd like to know more about this, but what does it mean that Revision V devices have an additional /2 ADC clock scaling? On the Cube MX's Clock Configuration screen, it is 50MHz, but will the frequency be further divided from here?
2023-10-23 07:14 PM
Take a look at the reference manual at the 25.4.3 ADC clocks section to see how the ADC clock is derived. This is the clock figure for the V revision. The Y revision does not have this divisor.
To find out what hardware revision you have, you can read the REV_ID field from the device.
You can read this field with the HAL_GetREVID() function and adjust your ADC prescaler accordingly.
if (HAL_GetREVID() == REV_ID_V) {
// prescaler 2
} else {
// prescaler 4
}
CubeMX also has a setting you're supposed to set based on the revision. Not sure how this plays into code generation.
2023-10-23 10:19 PM
I understand that the device I am using is V revision and it is working as configured.
Thank you for your detailed explanation. Thank you very much for helping me.