STM32H753XI. When 2 DMAs are working and writing data from SPI1/2 to SRAM1/2 the received data has errors. When only one DMA is working the received data has no errors. Why?

[nHasi.1]

I am using STM32h753XI.

The MCU uses 2 SPI channels (SPI1 and SPI2) in slave receive mode.

The MCU uses 2 DMAs channels (DMA1 stream0 and DMA2 stream0) to read the data from SPI1 and SPI2 and write it to SRAM1 and SRAM2 respectively.

The input SPI sclk is about 50 MHz

The 2 DMAs work continuously (circular mode).

The 2 DMAs FIFO is enabled.

The SPIs data word length is 32 bits.

The DMAs data width is 32 bits.

MCU Data Cache is disabled.

When the 2 DMAs work together the received data has few errors (1-10 in 10 seconds).

It sometimes seems like the data from SRAM1 had "leaked" to SRAM2 (I am not sure).

When I disable one of the DMA channels the received data has no errors at all.

What can be the reason for the data corruption when the 2 DMAs works simultaneously? 

[MM..1]

Something from other threads

Primary buffers must be global aligned.

The answer to the question: DMA1 and DMA2 have no conflict; the reason for the garbled code is that the sent buffer is a local variable defined in the function; the data has been tampered with for unknown reasons; it is sent garbled code; the buffer has not changed during the actual single-step debugging; maybe It is because of the following reasons: 1. The compiler optimizes the buffer, 2. The data is lost after the high-priority interrupt is interrupted; after the buffer is defined as a global variable, there is no garbled code sent;

but encountered another BUG, ​​which is the I2S in the project. DMA and SPI are both enabled for DMA transmission; because DMA1 is always a bus to access peripherals; when I2S is collecting data and sending data, the DMA transmission request of SPI will send bus arbitration and start SPI data transmission; cause the I2S audio stream to be interrupted; Consider changing the hardware circuit; move SPI to DMA2. Or lower priority.

At this point, the problem is over.

Try show some code too.

[Tesla DeLorean]

Speed, considering decimation, doesn't seem unduly fast for multiple memories, or multiple controllers.

Shouldn't be cache coherency if they are off, but that will make everything very slow.

What stepping / version of the core is in this part?

Any Errata look like this?

[nHasi.1]

Hi

Thank u both (Tesla and MM1) for the help.

• The buffers are defined as global and are aligned;

__attribute__((section(".sram1"))) volatile  ALIGN_32BYTES(uint32_t buff_sram1[32768]); /*buffer for 1st spi channel. located in SRAM1 (limit size 128KB <--> 32KW32)*/

__attribute__((section(".sram2"))) volatile  ALIGN_32BYTES(uint32_t buff_sram2[32768]); /*buffer for 2nd spi channel. located in SRAM2 (limit size 128KB <--> 32KW32)*/

• I tried to reduce the compiler optimization for 0. There is no change
• Tesla. STM32H753XIH6 version V. The is no relevant issue according to the errata.

Any more ideas?

Regards

[AScha.3]

just...i would try:

use 2 ch on same DMA ; ie. DMA1 stream0 and DMA1 stream1 .

[waclawek.jan]

> It sometimes seems like the data from SRAM1 had "leaked" to SRAM2 (I am not sure).

How do you know? How do you test it?

First make sure you know what da​ta you expect to see and that you observe them correctly.

JW​