STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

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STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM

the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

[Tesla DeLorean]

https://www.st.com/resource/en/datasheet/stm32h750ib.pdf

One is designed to clock at 400 MHz the other at 480 MHz

You should be able to identify the version.

SDRAM apt to be a sub-multiple, ie 66, 80, 100, or 120 MHz

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Well the Y's implicitly slower because the max CPU clock is 400

The slew-rate is impacted by the actual load presented.

Most of the SDRAM pin examples have SPEEDR eased back so the lines/traces don't ring.

Run both implementations at 400 / 100 MHz you won't have an issue.

Remember the FMC implementation is in cycles, you'd have to round and convert those to meet ns specs of memories.

SDRAM FMC should run in a DIV2 or DIV3 mode, as I recall

The memory here is also cacheable, and only really very efficient for burst access.

One of your options here is to clock the V at 440 MHz, or the SDRAM slower, I think you'd need to benchmark or characterize your implementation to understand the edges of the envelope.

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Thanks ,i am from hw side i am still understanding datasheet

but with rev V sample when we run 90MHZ or 99 MHZ it will work but above 100MHZ , SDRAM have 1 bit error in data but datasheet says we can run @110MHZ

here is clock PLL from FW team

t does dome from a PLL. We're feeding the PLL with the 25MHz crystal, then dividing by 5.

For the 115MHz option we multiply by 138 and divide by 2 in the PLL to give the FMC 345MHz.

The FMC then divides that by 3 for 115MHz FMC_CLK.

For the 107.5MHz option we multiply by 172 and divide by 4 in the PLL to give the FMC 215MHz.

The FMC then divides that by 2 for 107.5MHz FMC_CLK.

Similarly for the 90MHz option we multiply by 144 and divide by 4 in the PLL to give the FMC 180MHz.

The FMC then divides that by 2 for 90MHz FMC_CLK.

[Tesla DeLorean]

>> but datasheet says we can run @110MHZ

Not sure it does, it implies that they tested / characterized it on their implementation, not yours. As frequency increases signal integrity issues will be a big issue, and what loads are being driven/over-come. You might want to engage with an FAE, and find out what platform they validated the 110 MHz operation on.

That it's not 120 MHz suggests there's either a critical path, or the IO cell has a drive / energy issue, as there's plenty of SDRAM on the market capable of 133 or 166 MHz operation, I'm prone to think it's an internal or interface limitation.

That yours hits the ceiling at ~100 MHz suggests there's perhaps a board level integrity issue, or that you need to adjust or back-off the slew rate, or check the IO Cell Compensation

[Tesla DeLorean]

>>  FMC 345MHz

The peripheral has a 300 MHz ceiling with VOS0, 250 MHz at VOS1 (RM0433 Rev 😎

Likely these come from an analysis of internal nets for critical paths, vs switching speeds, and propagation.

You could likely just clock at ~220 MHz from PLL_R

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do you think NOR flash load capacitance of 10 pf also limiting frequency for SDRAM to run at limit