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Ssaga.1 · 2023-02-21

STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAMthe datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

Ssaga.1 · 2021-08-23

how can i program EXternal STM32 Board using silicon lab Wireless Starter Kit with the BRD4151A Radio Board. ?

Ssaga.1 · 2023-03-09

do you think NOR flash load capacitance of 10 pf also limiting frequency for SDRAM to run at limit

Ssaga.1 · 2023-02-28

Thanks ,i am from hw side i am still understanding datasheet but with rev V sample when we run 90MHZ or 99 MHZ it will work but above 100MHZ , SDRAM have 1 bit error in data but datasheet says we can run @110MHZ here is clock PLL from FW team t does...

Ssaga.1 · 2023-02-21

Ssaga.1 · 2023-02-21

STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAMdatasheet says 2 value for rev V and REV Y

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STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

how can i program EXternal JLINK STM32 Board using silicon lab Wireless Starter Kit with the BRD4151A Radio Board

Re: STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

Re: STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

Re: STM32H750IBK6 REV V sample what is max FMC CLK we can run SDRAM the datasheet says 2 different values for rev V and REV Y IC revision what is safe area of operating FMC CLK with SDRAM

Re: How to set up the FMC peripheral to interface with the SDRAM IS42S16800F-6BLI from ISSI