STM32H750 SAI interfaces

[MikeDB]

It was suggested I look at this part as it's definitely superior to the F730. However I can't see how to use the SAI4 interface because its SCK_A and SCK_B pins are shared with those of SAI1. Am I missing something or does this preclude using both SAI1 and SAI4 as masters ?

Also the datasheet has SAI4 on the APB4 bus and shown without a FIFO. Is this just a typo or is SAI4 really a different beast ?

Finally the H750 adds the concept of having D1-4 on the SAI1 and SAI4 interfaces but there's nothing in the datasheet or any presentation I can find on how to use these rather than the traditional SD_A and SD_B pins. Any links most appreciated.

[Amel NASRI]

Hello @MikeDB​ ,

SAI pins mapping in the datasheet is correct, so you are right: SAI1 and SAI4 share same pins.

This way, you cannot use 4 blocks as masters.

However, You can do following configuration for example:

• SAI1_A: Master
• SAI1_B: Synchrounous Slave
• SAI4_A: Synchronous Slave
• SAI4_B: Master

Having SAI1 and SAI4 mapped on same pins while being in different domains has as advantage to be able to reduce power consumption when turning off D2 to switch to SAI4 on D3, keeping the same pins (interfacing a codec for example).

If your requirement is to use 4 blocks as masters, you can select SAI2 instead of SAI4.

>> Also the datasheet has SAI4 on the APB4 bus and shown without a FIFO.

==> This needs to be fixed in the datasheet (as well as datasheets of other STM32H7 devices embedding SAI4) : SAI4 has a FIFO as others SAIs.

>> Finally the H750 adds the concept of having D1-4 on the SAI1 and SAI4 interfaces

==> We Have only D1-3. This is an error in both the reference manual and AN5027 and will be fixed.

-Amel

[MikeDB]

Thanks - that's helped a lot. And reassured me about the FIFO as without it there would be too much risk of jitter.