STM32H750 Quad SPI Flash memory mapped mode. error: data is 0x88.

[Andex]

Hello everyone!
I use the Quad SPI flash of stm32 h750. I write data at a certain address through commands, such as address 0. But after configuring the memory mapping mode, I check that the data at address 0x90000000 is 0x88, while my data is at 0x90000001.

more info:
Use Keil MDK software 

My operation:

1.Config Quad SPI

2.Write data (0xAB) to address 0

3.Read data in addre 0 (success)

4.Set memory mapped mode

5.Read data in 0x90000000, data is 0x88(error)

I have two questions：

1.After I write data to  address, in the memory mapping mode, the data is at address +1（byte）, is this normal?

2.Why can't the operation reach address 0？Seems to be caused by problem 1

Thanks!

My code:

void QUADSPI_Init(void)
{
    /* QUADSPI parameter configuration*/
    stQSpi.Instance = QUADSPI;
    stQSpi.Init.ClockPrescaler = 1;                                 
    stQSpi.Init.FifoThreshold = 4;                                  
    stQSpi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;    
    stQSpi.Init.FlashSize = POSITION_VAL(0X100000)-1;              
    stQSpi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;     
    stQSpi.Init.ClockMode = QSPI_CLOCK_MODE_0;               
    stQSpi.Init.FlashID = QSPI_FLASH_ID_1;                        
    stQSpi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;                 
    if (HAL_QSPI_Init(&stQSpi) != HAL_OK)
    {
        Error_Handler();
    }
}

void QSPI_Config_Mmap(void)
{
    QSPI_CommandTypeDef Cmdhandler;
    QSPI_MemoryMappedTypeDef stMMPCfg;
    
    stMMPCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
    stMMPCfg.TimeOutPeriod = 0;
    
    Cmdhandler.Instruction = 0xEB;                      //Quad IO Fast Read   
    Cmdhandler.Address = 128;
    Cmdhandler.DummyCycles = 4;
    Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
    Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
    Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
    Cmdhandler.DataMode = QSPI_DATA_4_LINES;
    Cmdhandler.SIOOMode=QSPI_SIOO_INST_EVERY_CMD;				
    Cmdhandler.AlternateByteMode=QSPI_ALTERNATE_BYTES_NONE;		
    Cmdhandler.DdrMode=QSPI_DDR_MODE_DISABLE;					
    Cmdhandler.DdrHoldHalfCycle=QSPI_DDR_HHC_ANALOG_DELAY;

    HAL_QSPI_MemoryMapped(&stQSpi,&Cmdhandler,&stMMPCfg);
}


void QspiFlash_Write_Page(uint8_t * pBuffer,uint32_t nWriteAddr, uint16_t nByteNum)
{
    stQSPI_CommandSet stCmdSet;
    
    QspiFlash_Write_Enable();					
  
    stCmdSet.nCmd=QSPI_FLASH_QuadPageProgram;   
    stCmdSet.nInstructionMode = QSPI_INSTRUCTION_1_LINE;
    stCmdSet.nAddrMode = QSPI_ADDRESS_1_LINE;
    stCmdSet.nAddress = nWriteAddr;
    stCmdSet.nAddrSize = QSPI_ADDRESS_24_BITS;
    stCmdSet.nDataMode = QSPI_DATA_4_LINES;
    stCmdSet.nDummyCycles = 0;
    QSPI_Send_CMD(stCmdSet);	
    QSPI_Transmit(pBuffer,nByteNum);	         	      
    QspiFlash_Wait_Busy();					   
} 

[Andreas Bolsch]

Maybe incorrect flash parameters ... But as you keep the type of flash device secret ...

[Tesla DeLorean]

0x88 suggests the device isn't in the mode expected or the command in not compatible with the device or mode.

You can't write whilst in memory mapped mode, or use the waiting methods, need to QSPI Abort to break out of Memory Mapped Mode.

You should test using the same command / structure in direct mode.

Device not identified, none of the initialization sequence shown.

[Ayoub Cheggari · Accepted solution]

Hi Andex,

This reminds me of the first time I used this mcu with that NOR flash! I suppose you are using the STM32H750-DB.

I think the issue here is the Dummy Cycles in Memory Mapped Function, it should be 6 not 4, with that, you have skipped 1 byt (2 * 4 = 8bits = 1byte)

This is from the Dayasheet!

[Andex]

Hi Ayoub:

I'm very thank you for helping me solve this problem.
When I set 6-dummy clock, the data is normal!

But I check the sequence diagram is, and maybe it includes 'M0-M7' clock-bit?:

[Andex]

I found a table about the dummy clocks.

[Ayoub Cheggari]

Happy to know you resolved the issue!

That dummy cycle is actually adjustable by a register which I don't remember its name!

[Tesla DeLorean]

If this is the STM32H750-DISCO/DK, then the MT25TL01G (dual-die). Both die get accessed in a ping-pong fashion at the byte level, and you need to read the status as a 16-bit word rather than 8-bit.

https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25t/generation-b/mt25t_qljs_l_512_xba_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500

https://github.com/STMicroelectronics/stm32-mt25tl01g