Hi Team,
Working on a custom design using STM32H750 and 2 Winbond W989D6DBGX6E LPSDR memory devices configured for 32b bus.
The Design passes memory test at FMC_SDCLK@80Mhz.
The Design fails memory test at FMC_SDCLK@100Mhz.
When checking the signal timing, FMC_SDNWE was observed as marginal.
The design configured I/O High Speed Low voltage and I/O compensation.
Checking the IO types for FMC_SDNWE io pins, the pin options DO NOT indicate the pin is _h type for High speed low voltage.
What would be the cause of the timing violation?
